Static information storage and retrieval – Read/write circuit – Testing
Patent
1994-01-27
1995-01-24
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Testing
3652257, G11C 2900
Patent
active
053847415
ABSTRACT:
A semiconductor memory device having a circuit for preventing the operation of a test mode includes a first terminal for receiving an externally applied high voltage exceeding a power supply potential, a second terminal for receiving an externally applied test mode signal and a high voltage detector for detecting that a high voltage signal has been applied through the first terminal. A test mode signal holding circuit is responsive to the high voltage detector and holds the test mode signal applied through the second terminal. A test circuit is responsive to the test mode signal held in the test mode signal holding circuit and performs a test in the semiconductor memory device. A disabling circuit is provided to disable the high voltage detector.
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Arita Yutaka
Haraguchi Yoshiyuki
LaRoche Eugene R.
Mai Son
Mitsubishi Denki & Kabushiki Kaisha
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