Semiconductor memory device adapted for preventing a test mode o

Details Semiconductor memory device adapted for preventing a test mode o Semiconductor memory device adapted for preventing a test mode o

1993-04-23

1994-04-19

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

3652257, 3652335, G11C 2900

Patent

active

053052676

ABSTRACT:
When a pre-shipment test of a SRAM is requested, a pulse signal PL having a pulse width exceeding a predetermined time length is applied through a terminal 62. A pulse width detecting circuit 80 detects the pulse width of the applied pulse signal to provide a holding signal HD. A test mode signal holding circuit 90 holds an externally applied test mode request signal TM' in response to the holding signal HD. After the completion of the pre-shipment test, pulse width detecting circuit 80 is disabled by a fusion of a fuse 71. Fuse 71 is fused after the pre-shipment test is conducted, whereby the test mode operation is prevented from undesirably occurring.

REFERENCES:
patent: 4956816 (1990-09-01), Atsumi et al.
patent: 5023840 (1991-06-01), Tobita
patent: 5132937 (1992-07-01), Tuda et al.
patent: 5155704 (1992-10-01), Walther et al.
patent: 5233610 (1993-08-01), Nakayama et al.

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