Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2002-05-14
2003-09-23
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C365S189080
Reexamination Certificate
active
06625050
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices. In particular, the invention relates to a semiconductor memory device having a pad arrangement, a circuit arrangement and a circuit structure adaptable to various types of packages.
2. Description of the Background Art
In recent years, semiconductor memory devices have been increasing in capacity and decreasing in package size for achieving a higher packaging density. BGA (Ball Grid Array) package and MCP (Multi Chip Package) are examples of such small-sized packages.
For a BGA-packaged semiconductor memory device, bonding pads are arranged on the peripheral region in consideration of the structure of BGA. For a MCP semiconductor memory device, bonding pads are also arranged on the peripheral region for stacking semiconductor chips on each other.
On the other hand, for a TSOP (Thin Small-Outline Package) semiconductor memory device, bonding pads are arranged on the central region in an LOC (Lead On Chip) structure since the TSOP uses a leadframe and thus it is difficult to design the leadframe if the pads are arranged on the peripheral region.
FIG. 28
shows an arrangement of pins of a TSOP for a DRAM (Dynamic Random Access Memory) with the ×32-bit configuration. The pins include power supply-related pins (denoted by VDD, VSS, VDDQ and VSSQ), data pins (denoted by DQi), address pins (denoted by Ai) and control signal pins (denoted by CLK, CKE, AE, RAS, CAS, CS and the like), and these pins are arranged along the two sides. Here, reference character
13
A is shown that is described later.
FIG. 29
shows a corresponding conventional arrangement of pads of a DRAM with ×32-bit configuration adapted for the TSOP shown in FIG.
28
. This DRAM adapted for the TSOP has pads arranged on the central region in the same order as that of pins of the package.
Different pad arrangements have been used for conventional semiconductor memory devices depending on the packaging type of the semiconductor devices. This is undesirable in terms of reduction in production cost and adaptation to various types of products.
Here, a semiconductor memory device is considered from its word structure. If the semiconductor memory device has a ×32-bit configuration which results in a high pin count and its TSOP of the ×32-bit configuration is implemented by arranging pads on the periphery, for example, the device size would increase as a whole since there should be left a sufficient space for the leadframe.
On the other hand, a semiconductor memory device of ×16-bit or less accordingly has a lower pin count. In this case, pads are desirably arranged on the periphery if a BGA package or MCP of ×16-bit configuration is employed. In addition, pads are desirably arranged along two sides only if the MCP is employed.
Regarding this issue, the number of pins is defined as “high pin count” or “lower pin count” depending on whether the bit number is
32
or
16
. If a further miniaturization is achieved in the future, a similar problem could arise in semiconductor memory devices of ×32-bit configuration and ×64-bit configuration and semiconductor memory devices of a greater number of bits.
Accordingly, as packaging density has been increasing in recent years, semiconductor memory devices should be adaptable to various types of packages and also adaptable to packages of smaller size.
SUMMARY OF THE INVENTION
The present invention is made to solve the problems as described above. One object of the present invention is to provide a semiconductor memory device adaptable to various types of packages.
Another object of the present invention is to provide a semiconductor memory device adaptable to any of different word structures.
Still another object of the present invention is to provide a semiconductor memory device with its package reduced in size while achieving the objects above.
According to one aspect of the present invention, a semiconductor memory device rectangular in shape and adaptable to various types of packages includes a memory element storing externally supplied data and a plurality of bonding pads for conveying power supply, data and a signal to/from the memory element. The bonding pads include a first power supply pad and a first ground pad and other bonding pads except for the first power supply pad and the first ground pad. The first power supply pad and the first ground pad are placed near the center of each of two opposite sides of the semiconductor memory device, and other bonding pads including a second power supply pad and a second ground pad are arranged on a peripheral region along remaining two sides other than the two opposite sides.
Preferably, when the semiconductor memory device is packaged by a TSOP, the first power supply pad is used by being wired to a lead of a leadframe that provides external power supply and the first ground pad is used by being wired to a lead of the leadframe that is grounded. When the semiconductor memory device is packaged by a BGA package or multichip package, the second power supply pad is used by being wired to a lead of the leadframe that provides external power supply and the second ground pad is used by being wired to a lead of the leadframe that is grounded.
Preferably, the semiconductor memory device has its word structure switchable between a first word structure and a second word structure larger than the first word structure. When the semiconductor memory device is used for the first word structure, the second power supply pad and the second ground pad are used by being wired respectively to a lead of a leadframe that provides external power supply and a lead of the leadframe that is grounded. When the semiconductor memory device is used for the second word structure, the first power supply pad and the first ground pad are used by being wired respectively to a lead of the leadframe that provides external power supply and a lead of the leadframe that is grounded.
Preferably, the memory element includes a memory cell array having a plurality of memory cells, an input/output circuit connected to a data input/output pad included in the bonding pads for input/output of data from/to external circuitry, and a data bus for transmitting data between the memory cell array and the input/output circuit. The memory cell array is formed of four banks arranged respectively in four regions of the semiconductor memory device, the four regions corresponding to respective regions generated by dividing the semiconductor memory device along a vertical central line and a horizontal central line. The input/output circuit is placed on the peripheral region along the remaining two sides where a line of the bonding pads is placed. The data bus is placed between the banks and along the remaining two sides. The banks are each connected to the data bus placed on a central region between the banks and extending in parallel with the remaining two sides.
According to another aspect of the present invention, a semiconductor memory device having a switchable internal power supply voltage and a switchable interface voltage includes a first switch signal generating circuit generating a first switch signal for switching the internal power supply voltage, a second switch signal generating circuit generating a second switch signal for switching the interface voltage, an internal power supply generating circuit converting, according to the first switch signal, an external power supply voltage to a predetermined internal power supply voltage and outputting the predetermined internal power supply voltage to an internal power supply node, and an input circuit changing, according to the second switch signal, a threshold of voltage determining a logic level of an external input signal. The first switch signal generating circuit includes a first bonding pad and generates the first switch signal according to whether or not a wire provided with a predetermined potential is connected to the first bonding pad. The second switch signal genera
Ishida Kozo
Jinbo Shinichi
Matsumoto Junko
Nagasawa Tsutomu
Okamoto Takeo
Dinh Son T.
McDermott & Will & Emery
Nguyen Hien
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