Semiconductor memory device achieving fast random access

Details Semiconductor memory device achieving fast random access Semiconductor memory device achieving fast random access

2003-03-21

2004-08-24

Lei, Thong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S189040

Reexamination Certificate

active

06781894

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices and particularly to a semiconductor memory device achieving fast random access.
2. Description of the Background Art
A semiconductor memory device disclosed in Japanese Patent Laying-Open No. 2000-268570 achieves fast data reading by allowing a read column selection signal to rise before a sense amplifier amplifies a potential difference between paired bit lines. The above-mentioned semiconductor memory device, however, fixes the potential of the source of a data-reading transistor.
Then, if the read column selection signal is raised before the sense amplifier amplifies the potential difference between paired bit lines, respective charges of paired read data lines having been precharged are both pulled down toward the ground and accordingly inputs to a preamplifier both have L (logical low) level. Therefore, data could not be read accurately in some cases.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a semiconductor memory device achieving fast random access as well as accurate reading of data all the time.
According to the present invention, a semiconductor memory device includes a memory cell array including a plurality of memory cells arranged in rows and columns, a plurality of word lines arranged correspondingly to respective rows of the memory cells and a plurality of pairs of bit lines arranged correspondingly to respective columns of the memory cells, a sense amplifier provided correspondingly to each of the pairs of bit lines, and a read gate circuit provided correspondingly to each of the pairs of bit lines and connected to a pair of read data lines for reading data. The read gate circuit includes a first transistor having its gate connected to one bit line of the corresponding pair of bit lines and its source dynamically changed according to activation/inactivation of the sense amplifier, and a second transistor having its gate connected to the other bit line of the corresponding pair of bit lines and its source dynamically changed according to activation/inactivation of the sense amplifier.
According to the present invention as discussed above, respective sources of the transistors in the read gate circuit are dynamically changed according to activation/inactivation of the sense amplifier to achieve fast random access as well as accurate reading of data all the time.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 6324110 (2001-11-01), Leung et al.
patent: 6560148 (2003-05-01), Takami et al.
patent: 2002/0015344 (2002-02-01), Leung et al.
patent: 2002/0136051 (2002-09-01), Hardee et al.
patent: 2000-268570 (2000-09-01), None
“A 1.5V Circuit Technology for 64Mb DRAMs,” Y. Nakagome et al., Symposium on VLSI Circuits, 1990, pp. 17-18.

Affiliated with

Also associated with

Rating

Semiconductor memory device achieving fast random access does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device achieving fast random access, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device achieving fast random access will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3286858