Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-12-23

2004-08-31

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S220000, C365S221000

Reexamination Certificate

active

06785172

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present intention relates to a semiconductor memory device having a test circuit.
2. Description of the Related Art
Test circuits internally provided in LSIs include those disclosed Japanese Unexamined Patent Publication No. 1987-31100 (Reference 1), Japanese Unexamined Patent Publication No. 1998-21109 (reference 2) and Japanese Unexamined Patent Publication No. 1998-78475 (Reference 3).
The test circuit disclosed in Reference 1 allows either a “read data through mode” or a “shift-functioning latch mode” to be selected. When the LSI is engaged in normal operation, the test circuit is set in the read data through mode. In this mode, the test circuit allows the data read out from a memory circuit (a semiconductor memory device) to pass through to be output to the outside of the LSI. When testing the LSI, the test circuit is set in the shift-functioning latch mode. At this setting, the test circuit temporarily stores therein the data read out from the memory circuit and then serially outputs the stored data. A decision can be made as to whether or not the data read out from the memory circuit match an expected value by observing the serial data.
The test circuit disclosed in Reference 2 allows an address signal that has been input therein to pass through to be provided to the memory circuit while the LSI is engaged in normal operation. During a test operation of the LSI, however, the test circuit converts a serial signal that has been input to a parallel signal and provides the parallel signal to the memory circuit as an address signal. This structure enables the test circuit to provide any address signal to the memory circuit.
By utilizing the test circuit disclosed in Reference 3, it becomes possible to provide any address signal and/or data to the memory circuit. In addition, the data read out from the memory circuit can be converted to a serial signal and then be output to the outside.
A semiconductor memory device normally comprises two separate components, i.e., a memory cell array unit having a plurality of memory cells are arranged in an array and a memory circuit internal logic unit. The memory circuit internal logic unit includes an address decoder, a column selector and like. By using a test circuit in the related art, an arbitrary address signal can be set at the memory circuit, data output from the memory circuit can be verified and arbitrary data can be written into the memory circuit. However, the test circuit in the related art tests the overall memory circuit, and the logic unit within the memory circuit is not specifically tested in the scan test. This gives rise to a problem in that even when normal results are obtained through a test conducted on a semiconductor memory device, it is difficult to pinpoint the exact location where the problem has occurred and thus, it is difficult to clarify the problem or to reassess the circuit at the design level.
SUMMARY OF THE INVENTION
An object of the present invention, which has been completed by addressing the problem of the related art discussed above, is to provide a new and improved semiconductor memory device whose memory cell array unit and memory circuit internal logic unit can be tested independently of each other.
In order to achieve the object described above, in a first aspect of the present invention, a semiconductor memory device comprising a memory cell array unit that is constituted of a plurality of memory cells in which data are stored, an address signal generating unit that generates an address signal with an n-bit width to specify a single memory cell or a plurality of memory cells among the plurality of memory cells and an address signal test circuit unit that converts the address signal with the n-bit width output from the address signal generating unit to a serial signal for address signal observation and outputs the serial signal resulting from the conversion is provided. By observing the serial signal for address signal observation, a decision can be made as to whether or not the address signal output from the address signal generating unit is normal.
In addition, the address signal test circuit unit may achieve a function of converting a test address several signal provided from the outside to a test address signal with the n-bit width and a function of taking in the address signal from the address signal generating unit and then providing either the test address signal or the address signal to the memory cell array unit so that an arbitrary address signal can be provided to the memory cell array unit by bypassing the address signal generating unit.
In a second aspect of the present invention, a semiconductor memory device comprising a memory cell array unit constituted of a plurality of memory cells in which data are stored, a data input/output unit achieving a function of outputting data with an m-bit width to be written into the memory cell array unit and a function of reading out data with the m-bit width from the memory cell array unit and a data test circuit unit that converts the data with the m-bit width read out from the memory cell array unit to a serial signal for data observation and outputs the serial signal resulting from the conversion, is provided. A decision can be made as to whether or not the data read out from the memory cell array unit match an expected value by observing the serial signal for data observation.
In addition, the data test circuit unit may achieve a function of converting a test data serial signal provided from the outside to a test data signal with the m-bit width and a function of providing the test data signal either to the memory cell array unit or the data input/output unit so that arbitrary data can be provided individually to the memory cell array unit or the data input/output unit.
If the semiconductor memory device adopts a structure in which a test address serial signal is provided to the data test circuit unit as a test data serial signal by an address signal test circuit unit, it is no longer necessary to obtain the test data serial signal from the outside. Likewise, if the semiconductor memory device adopts a structure in which the test data serial signal is provided to the address signal test circuit unit as a test address serial signal by the data test circuit unit, it is no longer necessary to obtain the test address serial signal from the outside.
The address signal test circuit unit may be constituted of a shift register. It is desirable that such a shift register be constituted of n flip-flops each corresponding to one of the bits in the test address signal and the address signal.
The data test circuit unit, too, may be constituted of a shift register. It is desirable that such a shift register be constituted of m flip-flops each corresponding to one of the bits in the data read out from the memory cell array unit and the test data signal. Alternatively, the shift register may be constituted of m sets of latch groups. Each latch group should include a first latch that latches input data in response to a signal indicating a logical high level and a second latch that latches the input data in response to a signal indicating a logical low level. The first latch or the second latch may be utilized as an output data latch function unit during a normal operation of the semiconductor memory device as well.
As described above, the present invention enables an operation function test to be conducted individually on the memory cell array unit, the address signal generating unit and the data input/output unit, independently of one another. As a result, it becomes possible to specify the exact location where the problem has occurred when abnormal results have been obtained in a test conducted on the semiconductor memory device. Furthermore, a problem latent in the semiconductor memory device manufacturing process can be clarified and the circuit can be reassessed at the design level with greater ease.


REFERENCES:
patent: 6570800 (2003-05-01), Tanaka et al.
patent: 2002/0149013 (2002-10-01), Sa

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