Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2003-05-29

2004-10-19

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including signal comparison

C365S210130, C365S205000

Reexamination Certificate

active

06807110

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2003-095399, filed Mar. 31, 2003, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly to a semiconductor memory device having a write operation function of transferring data to a bit line before a sense amplifier is activated.
2. Description of the Related Art
FIG. 11
schematically shows a part of a general DRAM (Dynamic Random Access Memory). A write operation of the DRAM is briefly described below. First, when one word line (e.g. word line W
0
) is selected, data output from a memory cell MC connected to the word line is read to complementary bit line pairs B
0
to B
7
. Then, potentials on the bit line pairs B
0
to B
7
are amplified by sense amplifiers SA
0
to SA
7
. When a column selection signal CSL
0
is supplied, write data is transferred to the bit line pairs B
0
to B
3
from a data line D. Because the bit line pairs B
4
to B
7
which are not selected perform normal read operations (hereafter, the refresh operation is executed), data is read to the bit line pairs B
4
to B
7
from the memory cell MC.
In the case of the data write, when data stored in the memory cell is different from data to be written in the memory cell, it is necessary to reverse potential relations between bit line pairs. Therefore, the write operation is delayed.
As one of measures for improving the delay, a write operation referred to as an early write operation is generally known. In the early write operation, data is transferred to a bit line pair before a sense amplifier is activated (before data from a memory cell is amplified) and the bit line pair is set to a potential corresponding to the data before a change of levels of the bit line pair starts to make a big change. Then, after the potential of the bit line pair is amplified, data is written in the memory cell. An example of the above technique is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2-226581.
The early write operation is also described as shown in FIG.
12
. First, a row address signal is fetched when an inversion signal of RAS falls. Then, an inversion signal of WRITE for designating the write operation is made to fall before an inversion signal of CAS for fetching a column address signal falls. According to the above control, the write data is transferred to the bit line pair before the sense amplifier is activated.
In a circuit shown in
FIG. 11
, the following problem occurs by executing the early write operation. First, attention is given to the boundary between the bit line pairs B
0
to B
3
to be controlled by a column selection signal CSL
0
and the bit line pairs B
4
to B
7
to be controlled by a column selection signal CSL
1
.
FIGS. 13A and 13B
show a state of the bit line pair B
4
(bit lines B
4
a
and B
4
b
) and a state of the complementary bit line pair B
3
(bit lines B
3
a
and B
3
b
) in the case where the column selection signal CSL
0
is supplied, respectively. In the case of write according to the early write operation, write of data in the bit line B
3
b
starts (rise of the potential of the bit line B
3
b
starts) before column selection at time T
2
as shown in FIG.
13
B. Before amplification starts (before time T
3
), the bit line B
4
a
at a low potential is easily influenced by the bit line B
3
b
. Particularly, when the potential relation between the bit lines B
3
b
and B
4
a
is reversed, the potential of the bit line B
4
a
is greatly influenced and a malfunction of a DRAM may occur. This problem becomes more remarkable as the distance between bit lines decreases due to improvement of a DRAM in integration degree and decrease of the DRAM in size.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: first and second bit lines to which data read from first and second memory cells are supplied, respectively, when a word line is activated; a first dummy bit line provided between the first and second bit lines without interposing any other bit line therebetween and fixed to the ground potential; first and second sense amplifiers which amplify potentials on the first and second bit lines, respectively; and a connection control section which controls so that write data is supplied to the first bit line or the second bit line after the word line is activated and before the first and second sense amplifiers operate.
According to a second aspect of the present invention, there is provided a semiconductor memory device comprising: a word line constituting gates of first and second memory cell transistors serving as parts of first and second memory cells and extending in a first direction; a wiring layer extending in the first direction above the word line and electrically isolated from the word line; first and second bit lines to which data read from first and second memory cells are supplied, respectively, when the word line is activated; first and second sense amplifiers which amplify potentials on the first and second bit lines, respectively; a connection control section which controls so that write data is supplied to the first bit line or the second bit line after the word line is activated and before the first and second sense amplifier operate; and a connection layer provided only between the first and second bit lines to electrically connect the word line with the wiring layer.
According to a third aspect of the present invention, there is provided a semiconductor memory device comprising: first to n-th (n is a natural number of 2 or more) bit line groups which are sequentially arranged so as to be adjacent to each other and respectively comprise a plurality of bit lines adjacent to each other along a first direction, data read from a plurality of memory cells respectively connected with the plurality of bit lines being read to the bit lines; a plurality of first dummy bit lines provided between the bit lines forming a boundary between an i-th (i is a natural number of 1 to n−1) bit line group and an (i+1)-th bit line group without interposing any other bit line and fixed to the ground potential; a plurality of sense amplifiers provided for each of the plurality of the bit lines, respectively, and amplifying potentials on the plurality of bit lines; and a connection control section which controls so that write data is supplied to one of the first to n-th bit line groups after the word line is activated and before the sense amplifiers operate.
According to a fourth aspect of the present invention, there is provided a semiconductor memory device comprising: a word line constituting gates of memory cell transistors serving as parts of memory cells and extending in a first direction; a wiring layer extending in the first direction above the word line and electrically isolated from the word line; first to n-th (n is a natural number of 2 or more) bit line groups which are sequentially arranged so as to be adjacent to each other and respectively comprise a plurality of bit lines adjacent to each other along a second direction different from the first direction, data read from a plurality of memory cells respectively connected with the plurality of bit lines being read to the bit lines; a plurality of sense amplifiers provided for each of the plurality of the bit lines, respectively, and amplifying potentials on the plurality of bit lines; a connection control section which controls so that write data is supplied to one of the first to n-th bit line groups after the word line is activated and before the sense amplifiers operate; and a connection layer provided only between the bit lines which form a boundary between an i-th (i is a natural number of 1 to n−1) bit line group and an (i+1)-th bit line group to electrically connect the word line with the wiring layer.


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