Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-09-26

2004-08-24

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S201000

Reexamination Certificate

active

06781862

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device (ferroelectric memory) which uses the polarization of ferroelectric capacitors, and, more particularly, to a semiconductor memory device which can ensure a shorter time to detect defective cells or a semiconductor memory device which can avoid a thermal inprinting phenomenon.
2. Prior Art
Some of conventional semiconductor memory devices which use the polarization of ferroelectrics are described in Document 1, “Low Consumption Power, Fast LSI Technology” (pp. 231-250, published on Jan. 31, 1998 by Realize Corporation), and Document 2, “Unerasable IC Memory—All About FRAM” (pp. 29-37, published on Jul. 9, 1996 by Kogyo Chosakai Publishing Co., Ltd.).
The operational methods for the semiconductor memory devices that use the polarization of ferroelectrics are classified into the 2T2C type and 1T1C type. Of those two types, the 2T2C type will be discussed first.
FIG. 14
is a structural diagram of a 2T2C type memory device, which comprises memory cells MC
0
and MC
1
formed by ferroelectric capacitors, select transistors T
0
and T
1
which connect the memory cells MC
0
and MC
1
to a bit line BL or a bit line complementary line BLb, a word line WL connected to the gates of the select transistors T
0
and T
1
, a plate line PL connected to the memory cells MC
0
and MC
1
and a sense amplifier SA which amplifies the difference between the potentials of the lines BL and BLb in response to an enable signal SAE.
FIG. 15
shows waveforms for explaining the read operation of the thus constituted 2T2C type memory device. In the case of the 2T2C type, when a word line potential WL rises, data in the memory cells MC
0
and MC
1
are transferred to the bit lines BL and BLb, so that 0 is written in one of the memory cells MC
0
and MC
1
and 1 is written in the other one. Suppose that 0 is written in the memory cell MC
0
and 1 is written in the memory cell MC
1
. When the word line potential WL rises at time t1 and a plate line potential PL rises at time t2, the charges in the memory cells MC
0
and MC
1
are distributed to the bit lines BL and BLb and take values of V0 and V1, respectively. At time t3, the enable signal SAE becomes active to enable the sense amplifier SA. As a result, the potential difference between the bit lines BL and BLb is amplified and data is read out.
FIG. 16
is an explanatory diagram of a 1T1C type memory device, which comprises memory cells MC
0
and MC
1
formed by ferroelectric capacitors, select transistors T
0
and T
1
which respectively connect the memory cell MC
0
to a bit line BL and the memory cell MC
1
to a bit line complementary line BLb, word lines WL
0
and WL
1
connected to the gates of the respective select transistors T
0
and T
1
, a plate line PL connected to the memory cells MC
0
and MC
1
, a sense amplifier SA which amplifies the difference between the potentials of the lines BL and BLb in response to an enable signal SAE and a Vref generating circuit which generates a reference voltage Vref.
FIG. 17
shows waveforms for the read operation of the 1T1C type memory device. In the case of the 1T1C type, only one of the word lines WL
0
and WL
1
rises. For example, when the word line WL
0
rises, the potential of the bit line BL takes a value of V0 and the voltage Vref generated by the Vref generating circuit is applied to the bit line complementary line BLb, so that the sense amplifier SA stores the potentials of the bit lines BL and BLb. The voltage Vref is applied to the bit line complementary line BLb when the word line WL
0
rises and the voltage Vref is applied to the bit line BL when the word line WL
1
rises, thus ensuring reading of data “0” and “1”.
FIG. 18
shows one example of a hysteresis loop of a ferroelectric capacitor where Qh
1
is a point corresponding to data “1” and Q
11
is a point corresponding to data “0”. Cb
1
(1) is a bit line capacitance when a voltage is not applied to the ferroelectric capacitor. When a voltage of VDD is applied to the ferroelectric capacitor, the bit line capacitance which has charges Qh
1
corresponding to data “1” is shifted to VDD. Because actually there is no increase or decrease in charges, therefore, the charges are redistributed between the bit line capacitance and the capacitance of the ferroelectric capacitor and the bit line capacitance is shifted to an intersection Qh
2
of a bit line capacitance Cb
1
(2) and the hysteresis loop. With regard to the point Q
11
corresponding to data “0”, the bit line capacitance is similarly shifted to a point Q
12
. A then differential potential &Dgr;V between V1 and V0 in the diagram is amplified by the sense amplifier SA and is read out.
FIG. 19
shows the relationship between &Dgr;V or the value of V1−V0 and Cb
1
. &Dgr;V takes a peak value depending on Cb
1
. Because the memory capacities of current semiconductor memory devices which use the polarization of ferroelectrics become larger or the number of memory cells connected to a single bit line becomes larger, Cb
1
takes a value greater than the peak value.
Inprinting of a ferroelectric capacitor is a phenomenon in which the hysteresis loop is shifted due to the constant voltage application to the ferroelectric capacitor or saving at a high temperature in a polarized state.
FIG. 20
shows hysteresis loops before and after inprinting. The solid line indicates the hysteresis loop before inprinting and the broken line indicates the hysteresis loop after inprinting to “0”. Inprinting to “0” shifts the hysteresis loop rightward to decrease both V0 and V1, thus making it difficult to read “1”. Inprinting to “1”, on the other hand, shifts the hysteresis loop leftward to increase both V0 and V1, thus making it difficult to read “0”.
FIG. 21
shows a flow from the end of a wafer process for a semiconductor memory device, such as DRAM, to the shipment. A wafer which has completed the wafer process is probed in the wafer state, then those devices which have passed are molded and the molds are subjected to a sorting test to sort out only those passed as good devices. Because molds are placed at a high temperature of about 170° C. for about three hours, if ferroelectric memories are sorted along this flow, write data at the time of probing is inprinted under the high molding temperature.
At the time of probing, ferroelectric capacitors degraded due to a process variation are checked out and the associated devices are discriminated as defective or redundancy saving is performed on the degraded ferroelectric capacitors. It is necessary, at this time, to perform a long cycling test in order to find out deteriorated ferroelectric capacitors.
According to the prior arts, as described above, when ferroelectric memories in the wafer state are probed and molding is carried out thereafter, thermal inprinting occurs so that molds suffer a low inprint resistance. Further, a cycling test must be performed to find ferroelectric capacitors degraded by a process variation, resulting in further degradation of the ferroelectric capacitors. This makes the overall test time longer.
Accordingly, the invention aims at providing a semiconductor memory device which solves the first problem that the conventional semiconductor memory devices using ferroelectric capacitors need a longer test time to detect degraded ferroelectric capacitors or a semiconductor memory device which solves the second problem of suffering a lower inprint resistance.
SUMMARY OF THE INVENTION
To overcome the first problem, a semiconductor memory device according to the invention is designed in such a way that a voltage VBL of a bit line pair which determines a voltage to be applied to ferroelectric memory cells and a voltage VPL of plate lines are so set as to satisfy a relationship of VBL=VPL<VDD where VDD is a supply voltage. This makes the size of the hysteresis loop of the ferroelectric capacitors smaller than that in case of VBL=VPL=VDD, a potential difference &Dgr;V between data “0” and data “1” can be

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3286304