Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1998-06-07

1999-05-25

Phan, Trong

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 36523003, G11C 700, G11C 800

Patent

active

059075155

ABSTRACT:
A structure of a redundant cell array applicable for a compression test in which a defective cell is detected by concurrently selecting cells in a plurality of segments is provided. In the structure of the redundant cell array in a semiconductor storage device according to the present invention, areas for the compression test in which data write and read are performed by concurrently selecting memory cells in a plurality of segments SGM can be replaced to a redundancy cell array 30. That is, at least, one part of addresses Y0 and Y1 decoded by a column decoder 40 is stored in a redundant ROM of a redundancy detector 34 and is replaced to the redundant cell array 30 when the addresses coincide with the stored address. In this case, at least, one part of the addresses Y2 and Y3 decoded by a segment decoder 50 is supplied to a redundant column decoder 36 provided for the redundant cell array 30.

REFERENCES:
patent: 4473895 (1984-09-01), Tatematsu
patent: 5740120 (1998-04-01), Okamura

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