Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2003-07-10

2004-10-12

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S068000, C257S071000, C257S296000, C257S298000, C257S324000, C438S003000, C438S240000, C365S158000

Reexamination Certificate

active

06803619

ABSTRACT:

CROSS-REFERENCE TO PRIOR APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-201166, filed on Jul. 10, 2002, the entire content of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to non-volatile magnetic memory devices using tunneling magneto-resistive (TMR) elements to achieve electromagnetic write and read capabilities.
2. Description of Related Art
Nonvolatile memory devices which electromagnetically perform data writing and reading include magnetic random access memory (MRAM) devices. To realize random accessing capabilities, MRAMs are typically designed to include rows and columns of electrical wiring lines, also known as “current magnetic field” lines. The rows of wiring lines cross over the columns of wiring lines at right angles to thereby provide a matrix of crossing points, with magneto-resistance effect elements laid out at the crossing points. By selecting one from among the rows of current magnetic field wiring lines while simultaneously selecting a column wiring line in a one-by-one manner, it is possible to read or write any given magnetic storage cell or bit.
Conventionally, the mainstream in the MRAM technology lies in memory cells using giant magneto-resistive (GMR) elements. Unfortunately, in a GMR element, a magneto-resistance (MR) ratio—a ratio of a resistance value when data “1” is written into a cell, to that when a data “0” is written into the cell—stays as small as several percent (%), Which is not sufficient to attain high performance memories. In contrast, tunneling magnetoresistive (TMR) operability at room temperature was confirmed in 1996, followed by the ascertainment of MR ratios over 40% at room temperature. Since then, the trend in MRAM cell research and investigation has shifted at a burst to TMR elements.
Typically a TMR element is designed to have a magnetic tunnel junction (MTJ) structure. This MTJ structure includes two magnetic layers—usually, ferromagnetic (FM) layers—sandwiching a insulating tunnel barrier layer. Binary information stored in the TMR element is defined by determining whether the spin directions of the two magnetic layers are parallel or anti-parallel to each other. Note here that the term “parallel” used in this context, and hereinafter, refers to a state that the two magnetic layers are identically the same in spin direction as each other, whereas the term “antiparallel” means that these layers are exactly opposite in spin direction to each other.
One of current magnetic field wiring lines which intersect with a TMR element interposed therebetween is an write word line, which serves for applying current magnetic field to the TMR element in a non-contact fashion. The other is an data select line (bit line), which is electrically connected to an electrode of the TMR element. Data writing is accomplished by causing current to flow in the write word line and the data select line and then setting the spin direction of a TMR element in either the parallel or the antiparallel state by a magnetic field as created by the current flowing in the both lines. Data read is done by detecting the value of a current flowing in a data select line to thereby sense that the TMR element is different in resistance depending upon the data being presently stored therein.
Great interest at present in research and development of MRAM devices is centered on establishment of advanced technologies that enable MRAMs using TMR elements stated above to be reduced to practice as LSI memory products. But many technical obstacles remain before TMR-MRAM chips will become practical. One representative obstacle to be overcome is the difficulty in providing a technique for fabricating a tunnel barrier layer which is as thin as 1 nanometer (nm) while guaranteeing increased reliability and, at the same time, ensuring well-stabilized TMR element operability. More specifically, in order to combine LSI technologies that have long been developed as silicon processes, and TMR film fabrication technologies that have been developed mainly for magnetic head applications, it is required to improve irregularity formed on an underlayer film during silicon processes to a level acceptable for a TMR film to be formed on the underlayer film.
FIG. 9
illustrates, in cross-section, an integrated structure of a conventional TMR-MRAM chip, which is found in R. Scheuerlein et al., IEEE International Solid-State Circuits Conference (ISSCC) 2000, Digest of Technical Papers, p. 128. The TMR-MRAM structure of
FIG. 9
includes TMR elements each of which is connected to a transistor formed above a silicon substrate
1
, although such transistors are not visible in the cross-section shown herein. Electrical wire leads
3
are the ones that continuously pattern the gate electrodes of the transistors. These wire leads
3
are on an element isolation dielectric film
2
in the cross-section of FIG.
9
. These leads
3
are for use as read word lines (R-WL).
The TMR elements VR are formed on an interlayer dielectric film
4
at locations overlying the transistors. The interlayer dielectric film
4
is such that a plurality of wiring layers are buried therein. A wiring lead
7
that is connected to upper surfaces of the TMR elements VR is for use as a read and write-use bit line (R/W-BL). A wiring lead
6
a
that is buried immediately beneath each TMR element VR is a write word line (W-WL), which is designed to extend perpendicular to the wiring lead
7
.
The individual TMR element VR has its lower electrode
8
, which is drawn to outside of the region of this TMR element VR for electrical interconnection with the source/drain diffusion layer of a transistor. This lower electrode
8
is connected to the transistor's source/drain diffusion layer through a contact plug
9
and also via relay wire
6
b
and
5
.
In the TMR-MRAM structure shown in
FIG. 9
, the width of each TMR element VR (width of magnetic tunnel junction or “MTJ”) and the width of the wire lead
6
a
which applies a write current magnetic field to this junction from its lower part are made almost equal to each other in order to minimize the resulting cell area. Unfortunately in LSI processes, misalignment can occur due to the execution of alignment of physically different layers during lithography steps. In
FIG. 9
, there is shown an example that the patterns of a TMR element VR and its underlying wire
6
a
are misaligned and offset by a degree corresponding to almost half of the width thereof. To facilitate the understanding of its influence, a part encircled by dotted line in
FIG. 9
is enlargedly depicted in a sectional diagram of FIG.
10
.
After having formed the TMR element VR's lower write-use wire lead
6
a
, its upper part is covered with the interlayer dielectric film
4
. However, a slant stair-step-like height difference portion remains at edge of wire
6
a
in most cases. The step-like difference portion typically measures several to several tens of nm. Creation of this step-like surface irregularity is unavoidable even when using methods for forming by patterning techniques the wires on or above the interlayer dielectric film or alternatively using methods for forming grooves in the interlayer dielectric film and then burying wire metals therein. And, such step-like surface difference is not completely “absorbed” even after deposition of an interlayer dielectric film thereon, resulting in appearance of a similar step-like surface configuration thereover—in other words, this portion is “inherited” as an underlayer step-like difference of TMR element VR. TMR element VR has two magnetic layers
11
and
13
with a tunnel barrier layer
12
sandwiched therebetween. This tunnel barrier
12
is an ultrathin film with its thickness of about 1 nm as stated previously. Thus, the presence of such underlayer step difference can seriously affect the reliability and operation characteristics of the tunnel barrier film.
Although in the TMR-MRAM cell structure of

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