Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-09-20

2004-05-25

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S230030, C365S230060

Reexamination Certificate

active

06741511

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly relates to a circuit configuration for driving an internal data line. More specifically, the present invention relates to a circuit configuration for accelerating a voltage stress between complementary internal data lines.
2. Description of the Background Art
FIG. 26
is a schematic diagram showing the configurations of a main part of a conventional semiconductor memory device. In
FIG. 26
, a memory array MA is divided into a plurality of memory sub-blocks MSB. Memory sub-blocks MSB are arranged in alignment in row and column directions. The memory sub-blocks arranged in alignment in the row direction constitute a row block RBK. In
FIG. 26
, memory array MA is divided into row blocks RBK
0
to RBKm along the column direction. In addition, memory sub-blocks MSB arranged in alignment in the column direction constitute a column block CBK. In
FIG. 26
, memory array MA is divided into column blocks CBK
0
to CBKn.
Write/read circuits PW
0
to PWn for writing/reading internal data are arranged corresponding to column blocks CBK
0
to CBKn, respectively. These write/read circuits PW
0
to PWn are connected to an input/output circuit IOK through a data bus DBS having a width of a plurality of bits.
In the semiconductor memory device shown in
FIG. 26
, data access is made on a column block basis. Among column blocks CBK
0
to CBKn, one or a plurality, a predetermined number, of column blocks are simultaneously selected, the write/read circuit(s) arranged corresponding to the selected column block(s) is/are selectively activated and the internal data is written/read to/from the selected column block(s).
In row selection, the selection of a memory cell row is performed on a row block basis. In this row selection, as in the case of the column selection, one or a plurality of row blocks are activated among row blocks RBK
0
to RBKn.
FIG. 27
is a schematic diagram showing the configurations of one memory sub-array MSB and associated internal data lines. In
FIG. 27
, the configuration of a section related to internal data lines transmitting 2-bit internal data is shown by way of example. The bus width of the internal data lines is desirably set.
In
FIG. 27
, memory sub-array MSB includes a plurality of memory cells MC arranged in a matrix of rows and columns, a plurality of bit lines BL and/BL each connecting to the memory cells in the corresponding column, and a plurality of word lines WL arranged corresponding to the memory cell rows, respectively and to each connecting to the memory cells in the corresponding row. Bit lines BL and/BL are arranged in pairs to transfer complementary data.
FIG. 27
representatively shows memory cells MC arranged in two rows and two columns, word lines WLa and WLb arranged corresponding to the memory cells in the two rows, respectively, and bit line pairs BLa, ZBLa and BLb, ZBLb arranged corresponding to the memory cells in the two columns, respectively.
Memory cells MC are arranged corresponding to the crossings between one of the paired bit lines BL and ZBL and word line WL, respectively. In
FIG. 27
, memory cells MC are arranged corresponding to the crossing between word line WLa and bit line BLa and that between word line WLa and bit line BLb, respectively.
Memory cell MC includes a capacitor MQ which stores information, and an access transistor MT which connects a corresponding capacitor MQ to a corresponding bit line BL or ZBL in accordance with a signal on a corresponding word line WL (which generically represents a word line). Here, bit lines BL and ZBL generically represent bit lines BLa, BLb and ZBLa, ZBLb shown therein, respectively. Access transistor MT consists of an N-channel MOS (insulated gate field effect) transistor.
A sense amplifier SA is arranged corresponding to bit line pair BL and ZBL. When a sense amplifier activation signal SAE is activated, sense amplifier SA is activated to differentially amplify and latch the potentials of corresponding bit line pair BL and ZBL. Sense amplifier SA normally includes a P-sense amplifier which consists of cross-coupled P-channel MOS transistors and an N-sense amplifier which consists of cross-coupled N-channel MOS transistors. Sense amplifier activation signal SAE, therefore, includes a signal which activates the P-sense amplifier and a signal which activates the N-sense amplifier.
A column select gate CSGa which connects bit lines BLa and ZBLa to local data lines LIO
0
and ZLIO
0
, respectively in accordance with a column select signal CSL, is arranged corresponding to bit line pair BLa and ZBLa. Likewise, a column select gate CSGb which is rendered conductive in accordance with column select signal CSL and which connects bit lines BLb and ZBLb to local data lines LIO
1
and ZLIO
1
, respectively, when conductive, is arranged corresponding to bit line pair BLb and ZBLb.
Local data lines LIO
0
, ZLIO
0
, LIO
1
and ZLIO
1
are arranged for each memory sub-block in each column block. In row block selection, local data lines LIO and ZLIO (which generically represent LIO
0
and LIO
1
, and ZLIO
0
and ZLIO
1
, respectively) arranged for the memory sub-blocks in the selected row block are connected to corresponding global data lines described later, respectively.
An equalization transistor LQ
0
responsive to a local data line equalization instruction signal LIOEQ is arranged for local data lines LIO
0
and ZLIO
0
. Likewise, an equalization transistor LQ
1
responsive to local data line equalization instruction signal LIOEQ is arranged for local data lines LIO
1
and ZLIO
1
. When conductive, equalization transistor LQ
0
electrically short-circuits local data lines LIO
0
and ZLIO
0
. When conductive, equalization transistor LQ
1
electrically short-circuits local data lines LIO
1
and ZLIO
1
.
Local data lines LIO
0
, ZLIO
0
, and LIO
1
, ZLIO
1
are electrically connected to global data lines GIO
0
, ZGIO
0
and GIO
1
, ZGIO
1
through IO select gates IOG
0
and IOG
1
, respectively. IO select gates IOG
0
and IOG
1
are rendered conductive when IO select signal IOSEL to be activated for a selected row block is activated, and connect, when conductive, corresponding local data lines LIO
0
, ZLIO
0
and LIO
1
, ZLIO
1
to global data lines GIO
0
, ZGIO
0
and GIO
1
, ZGIO
1
, respectively.
Global data lines GIO
0
, ZGIO
0
and GIO
1
, ZGIO
1
are arranged in common to the memory sub-blocks included in a column block. In the corresponding column block, one memory row block is selected with respect to global data lines GIO
0
, ZGIO
0
, GIO
1
and ZGIO
1
, and the local data lines provided for the memory sub-blocks included in the corresponding row block are electrically connected to the corresponding global data lines.
An equalization transistor GQ
0
which electrically equalizes global data lines GIO
0
and ZGIO
0
, and a pull-up circuit PUG
0
which pulls up the potentials of global data lines GIO
0
and ZGIO
0
in data read, are provided for global data lines GIO
0
and ZGIO
0
. Likewise, an equalization transistor GQ
1
and a pull-up circuit PUG
1
are arranged for global data lines GIO
1
and ZGIO
1
.
Equalization transistors GQ
0
and GQ
1
become conductive when a global data line equalization instruction signal GIOEQ is activated. When a column block select signal CBS is activated, pull-up circuits PUG
0
and PUG
1
are activated to pull up the potentials of global data lines GIO, ZGIO
0
and GIO
1
, ZGIO
1
to a power supply voltage level, to decrease the voltage amplitudes of global data lines GIO
0
, ZGIO
0
and GIO
1
, ZGIO
1
in data read, to transmit small amplitude read signals and to achieve high speed data read.
In data write, this column block select signal CBS is kept inactive for a selected column block. In accordance with write data, global data lines GIO
0
, ZGIO
0
and GIO
1
, ZGIO
1
are driven to a power supply voltage level and a ground voltage level, respectively.
Global data lines GIO, ZGIO
0
and GIO
1
, ZGIO
1
are driven in accorda

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