Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-12-19

2004-09-14

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Fet configuration adapted for use as static memory cell

C257S903000, C257S905000

Reexamination Certificate

active

06791200

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a memory cell structure of a full CMOS static semiconductor memory device (hereinafter, referred to as “SRAM (Static Random Access Memory)”).
2. Description of the Background Art
FIG. 8
shows a conventional layout configuration of a full CMOS SRAM memory cell which consists of six MOS (Metal Oxide Semiconductor) transistors. An SRAM memory cell of this type is disclosed by, for example, Japanese Patent Laying-Open Nos. 10-178110 and 2001-28401.
As shown in
FIG. 8
, a memory cell
1
includes six MOS transistors. Specifically, memory cell
1
includes NMOS transistors N
1
, N
2
, N
3
and N
4
which are formed on P wells on both sides of an N well and PMOS transistors P
1
and P
2
which are formed on the central N well.
NMOS transistor N
1
is formed in a crossing portion between an impurity diffused region
2
a
and a polysilicon wiring
3
b
, NMOS transistor N
2
is formed in a crossing portion between an impurity diffused region
2
d
and a polysilicon wiring
3
c
, NMOS transistor N
3
is formed in a crossing portion between impurity diffused region
2
a
and a polysilicon wiring
3
a
, and NMOS transistor N
4
is formed in a crossing portion between impurity diffused region
2
d
and a polysilicon wiring
3
d
. PMOS transistor P
1
is formed in a crossing portion between an impurity diffused region
2
b
and polysilicon wiring
3
b
, and PMOS transistor P
2
is formed in a crossing portion between an impurity diffused region
2
c
and polysilicon wiring
3
c.
PMOS transistors P
1
and P
2
are load transistors, NMOS transistors N
3
and N
4
are access transistors, and NMOS transistors N
1
and N
2
are driver transistors. Impurity diffused regions
2
a
to
2
d
are connected to upper layer wirings through contact holes
4
a
to
4
l.
In the layout configuration shown in
FIG. 8
, word lines are arranged in a lateral direction. Bit lines are arranged in a longitudinal direction.
FIG. 9
shows a layout configuration of memory cells
1
of two bits adjacent each other in the extension direction of bit lines.
Lower memory cell
1
shown in
FIG. 9
is obtained by arranging upper memory cell
1
to be inverted about the boundary line between upper and lower memory cells
1
. As shown in
FIG. 9
, a distance D1 between polysilicon wirings
3
a
and
3
b
is equal to a distance D2 between polysilicon wiring
3
b
and polysilicon wiring
3
b
of adjacent memory cell
1
.
Meanwhile, to highly integrate memory cells
1
, it is rather efficient to shorten the short edge of memory cell
1
rather than to shorten the long edge thereof. If memory cell
1
shown in
FIG. 8
is formed by using process technique of a gate length of, for example, 0.18 &mgr;m, then the length of the short edge of memory cell
1
is 1.4 &mgr;m and that of the long edge thereof is 3.6 &mgr;m, for example. If so, the area of memory cell
1
is 5.04 &mgr;m
2
.
Now, if it is assumed that memory cell
1
can be shortened by 0.1 &mgr;m in a long edge direction, the area of the shortened memory cell is 1.4 &mgr;m×3.5 &mgr;m=4.9 &mgr;m
2
and can be reduced by approximately 3%. On the other hand, if it is assumed that memory cell can be shortened by 0.1 &mgr;m in a short edge direction, the area of the shortened memory cell is 1.3 &mgr;m×3.6 &mgr;m=4.68 &mgr;m
2
and can be reduced by approximately 7%.
If memory cell
1
is reduced by the same length, it is more effective to do so in the short edge direction. To shorten memory cell
1
in the short edge direction, the distance D between polysilicon wirings
3
a
or
3
b
which serves as a gate and contact hole
4
b
,
4
c
or
4
d
may simply be shortened.
However, if distance D is shortened, it is disadvantageously impossible to secure a margin for a mask deviation or the like which may cause during the formation of polysilicon wirings
3
a
and
3
b
and contact holes
4
b
,
4
c
and
4
d.
SUMMARY OF THE INVENTION
The present invention has been achieved to solve the above-described problem. It is an object of the present invention to provide a semiconductor memory device capable of efficiently reducing a memory cell area while securing a mask margin for a mask deviation or the like during the formation of a polysilicon wiring, a contact hole or the like.
A semiconductor memory device according to the present invention, includes: a word line; a bit line extending in a direction orthogonal to an extension direction of the word line; first and second memory cells aligned in the extension direction of the bit line; first and second gates of first and second MOS transistors, respectively, formed in the first memory cell, extending in the extension direction of the word line and arranged to be away from each other in the extension direction of the bit line; and third and fourth gates of third and fourth MOS transistors, respectively, formed in the second memory cell, extending in the extension direction of the word line, and arranged to be away from each other in the extension direction of the bit line. The second and third MOS transistors are located in the vicinity of a boundary between the first and second memory cells, and a distance between the first and second gates differs from a distance between the second and third gates.
The distance between the gates in the extension direction of the bit line is normally set at a minimum dimension in light of a margin during manufacturing. Due to this, to provide different gate distances in the extension direction of the bit line, it is necessary to locally set the gate distances shorter than the minimum dimension. By locally setting the gate distances shorter, it is possible to reduce the length of the shorter side of the memory cell. It is thereby possible to efficiently reduce a memory cell area.
The distance between the first and second gates may be set shorter than the distance between the second and third gates, and the distance between the second and third gates may be set shorter than the distance between the first and second gates.
The above-described semiconductor memory device includes: an impurity diffused region extending in the extension direction of the bit line, and having the first, second, third and fourth gates extending thereon; a first contact section formed on the impurity diffused region located between the first and second gates; and a second contact section formed on the impurity diffused region located between the second and third gates. In this case, a size of the first contact section is set smaller than a size of the second contact section. The first contact section is preferably a contact section in which even the increase of contact resistance does not influence a read rate, e.g., a contact section which is formed on the impurity diffused region which become a storage node section.
Further, the above-described semiconductor memory device may include: an impurity diffused region extending in the extension direction of the bit line, having first, second, third and fourth gates extending thereon, and having a protrusion section (a bent section or a branched section) protruding in the extension direction of the word line between the second and third gates; a first contact section formed on the impurity diffused region located between the first and second gates; and a second contact section provided on the protrusion section of the impurity diffused region, and formed at a position shifted from a region between the second and third gates in the extension direction of the word line.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5100817 (1992-03-01), Cederbaum et al.
patent: 6300229 (2001-10-01), Tanaka et al.
patent: 6469400 (2002-10-01), Kumagai et al.
patent: 10-178110 (1998-06-01), None
patent: P2001-28401 (200

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