Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-07-08

2004-05-18

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185050

Reexamination Certificate

active

06738290

ABSTRACT:

RELATED APPLICATION
This application claims for priority from Korean Patent Application No. 2001-47478, filed on Aug. 7, 2001, the contents of which are herein incorporated by reference in their entirety.
TECHNICAL FIELD
This disclosure relates to a data storage device and, more particularly, to an electrically erasable and programmable flash memory device.
BACKGROUND OF THE INVENTION
An electrically erasable and programmable flash memory device continuously holds data even though a power is not applied. Particularly, a NAND-type flash memory device has a string structure in which a plurality of flash memory cells are serially connected to each other, so that it is appropriate for integration and can be offered at a low price. Therefore, the NAND-type flash memory device is used as a data memory of various portable products.
Recently, demand for flash memory devices has increased. One of the request is for enhancement of data input/output speed. By increasing a page size (or page depth) and a memory block size, the data input/output speed can be enhanced. The “page” is made of a group of memory cells selected at the same time as activation of one wordline, and is a basic unit of read and program operations. The “memory block” is in turn made of a group of a several pages, and is a basic unit of an erase operation.
Referring now to
FIG. 1
, a conventional NAND-type flash memory device includes a memory cell array
10
, a page buffer circuit (or data sensing and latching circuit)
14
, and a column decoder circuit
16
. The memory cell array
10
is made of a plurality of memory blocks BLK
0
-BLKn, (n being a positive integer) each including a plurality of strings. Each of the strings is made of a string selecting transistor SST coupled to a corresponding bitline (e.g., BL
0
), a ground selecting transistor GST coupled to a common source line CSL, and memory cells MC
15
-MC
0
serially connected between the string and ground selecting transistors SST and GST. The string selecting transistor SST, the memory cells MC
15
-MC
0
, and the ground selecting transistor GSL are coupled to a string selecting line SSL, wordlines WL
15
-WL
0
, and a ground selecting line GSL, respectively. Block selecting transistors BS
17
-BL
0
are commonly controlled by a block selecting signal BS.
A row selecting circuit
12
selects one wordline (or page) out of the wordlines WL
0
-WL
15
by controlling block selecting transistors BS
0
-BS
17
. The page buffer circuit
14
temporarily stores data to be stored in memory cells of a selected page or senses the data stored therein. The page buffer circuit
14
is made of a plurality of page buffers (or data sensing and latching blocks) each corresponding to columns (i.e., bitlines) associated with a selected page. The detailed operations of such a page buffer are disclosed in U.S. Pat. No. 5,712,818, the teachings of which are hereby incorporated herein. Data bits sensed from memory cells of a selected page are output from the memory device with a predetermined unit (e.g., byte unit: x8).
The page size and block size are decided with hardware while designing a flash memory. Unlike a NOR-type flash memory reading data by a random access of a byte (x8) or word (x16) unit, the NAND-type flash memory device senses or latches data with a page unit for a relatively long time (e.g., dozens of microseconds) using the page buffer circuit
14
. An nREx pin is toggled to fetch the latched data with a “x8” unit by a data processing system (e.g., CPU). Therefore, the NAND-type flash memory needs a relatively long latency in data reading. But a data output speed of the NAND-type flash memory is high once a page buffer circuit senses and latches data.
It is well known that each of the memory cells constituting a cell string is made of a floating gate transistor having a source, a drain, a floating gate, and a control gate. The control gate of the respective floating gate transistors is connected to a wordline. Since each of the memory cells constituting the cell string is made of the floating gate transistor, for the string and ground selecting transistors acting as a conventional NMOS transistor, the first polysilicon layer for a floating gate and the second polysilicon layer for a control gate must be electrically coupled. This is described more fully herein below.
Referring now to
FIG. 2
, wordlines and ground selecting lines of each memory block (e.g., an ith memory block and an (i+1)th memory block) are formed by a self-aligned manner. In the ith memory block BLKi, a floating gate and a control gate of a ground selecting transistor GSTi are electrically connected to each other by a metal M
1
(e.g., tungsten) in order to act as a conventional NMOS transistor. Likewise, in the (n+1)th memory block, a floating gate and a control gate of a string selecting transistor SSTi+1 are electrically connected to each other by the metal M
1
(e.g., tungsten) in, order to act as the conventional NMOS transistor.
To accomplish this, a contact hole is formed so that the polysilicon floating gate can be exposed. The contact hole is filled with a metal so that the polysilicon for a control gate and the polysilicon for a floating gate can electrically contact each other. A contact formed through these steps is so-called “butting contact”. In each of the memory blocks, the butting contact increases the layout area along a row or wordline. Furthermore, the butting contact increases the layout area along a string. Such a phenomenon can cause serious problems as integration density becomes high.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide a NAND-type flash memory device having a shared selecting line structure. Also, embodiments of the invention provide a reduced area shared by a butting contact of a string/ground selecting transistor.
A further understanding of the nature and advantage of the invention herein may be realized by reference to the specification and the attached drawings.


REFERENCES:
patent: 5508957 (1996-04-01), Momodomi et al.
patent: 5712818 (1998-01-01), Lee et al.

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