Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-12-21

2004-04-27

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having fuse element

C365S201000, C365S205000, C326S010000, C327S525000, C327S526000

Reexamination Certificate

active

06728158

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to a semiconductor memory device and more particularly to a semiconductor memory device having a redundant circuit for replacing defects by using programmable elements for storing a defect address value.
BACKGROUND OF THE INVENTION
As semiconductor devices are made with finer geometries, the memory capacity of a semiconductor memory device, such as a dynamic random access memory (DRAM), becomes increasingly large. As the size of device structures is decreased, such as in the memory array region, manufacturing defects are increased, thereby decreasing the product yield and increasing manufacturing costs. For this reason, it is essential to incorporate redundant circuits to replace one or more defective memory cells in a mass memory. A redundant circuit for a semiconductor memory device includes a redundant row or a redundant column, which can correspond to a normal row or normal column in the memory cell array. The redundant circuit also includes a structure for detecting an address match between the applied address and a stored defective address. When an address match is indicated the corresponding normal row or normal column is replaced with a redundant row or a redundant column. In this way, a semiconductor memory device having a defect can still be used as a good device and yield can be increased.
A description will now be given of conventional approaches for detecting whether or not the applied address, such as an external address, coincides with the stored defective address.
Referring now to FIG.
9
(
a
), a conventional defect detecting circuit is set forth in a block schematic diagram and given the general reference character
700
.
The conventional defect detecting circuit
700
detects an address match between the applied address (A
0
to An) and a stored defective address and generates a coincidence detection signal RE.
Conventional defect detecting circuit
700
includes a coincidence detecting circuit
700
A and an address transition detecting circuit
700
B. Coincidence detecting circuit
700
A detects the coincidence of an externally input address (A
0
to An) with a stored defective address. Coincidence detecting circuit
700
A is initialized in response to a reset signal &phgr;r every time a new externally input address is received. Address transition detecting circuit
700
B detects a change in the externally input address (A
0
to An) to generate the reset signal &phgr;r.
Referring now to FIG.
9
(
b
) coincidence detecting circuit
700
A is set forth in a circuit schematic diagram.
Coincidence detecting circuit
700
A includes a p-type field effect transistor TP
700
having a source connected to VDD, a drain connected to internal lode ND, and a gate connected to receive reset signal &phgr;r. P-type field effect transistor TP
700
forms a precharge path between internal node ND and VDD. For each address received, there are two discharge paths between internal node ND and VSS. For address A
0
, a first discharge path is formed by n-type field effect transistor TN
0
T and fuse F
0
T and a second discharge path is formed by n-type field effect transistor TN
0
N and fuse F
0
N. N-type field effect transistor TN
0
T has a source connected to VSS, a drain connected to a first fuse terminal, and a gate connected to receive true address A
0
T. Fuse F
0
T has a second fuse terminal connected to internal node ND. N-type field effect transistor TN
0
N has a source connected to VSS, a drain connected to a first fuse terminal, and a gate connected to receive complementary address A
0
N. Fuse F
0
N has a second fuse terminal connected to internal node ND. Similarly, N-type field effect transistors (TN
1
T-TN
1
N to TNnT-TNnN) and fuses (F
1
T-F
1
N to FnT-FnN), respectively, are configured to provide two discharge paths between internal node ND and VSS for each address (A
1
to An). However, only one of each of the two discharge paths is active at any time based on whether the corresponding address has a logic one or logic zero value. For example, if address A
0
is high, true address A
0
T is high and n-type field effect transistor TN
0
T is turned on and the discharge path formed by n-type field effect transistor TN
0
T and fuse F
0
T is turned on. Also, complementary address A
0
N is low and n-type field effect transistor TN
0
N is turned off, and the discharge path formed by n-type field effect transistor TN
0
N and fuse F
0
T is turned off. However, if address A
0
is low, complementary address A
0
T is high and n-type field effect transistor TN
0
N is turned on. Also, true address A
0
T is low and n-type field effect transistor TN
0
T is turned off and the discharge path formed by n-type field effect transistor TN
0
T and fuse F
0
T is turned off. Discharge paths that receive true and complementary address bits (A
1
T-A
1
N to AnT-AnN) are similarly configured.
Fuses that are programmed to indicate either a logic one or a logic zero for each address (A
0
to An) is programmed for the stored defective address. For example, if the stored defective address has an address A
0
that is a logic one, fuse F
0
T is blown or opened. Thus, when received address A
0
is high, true address TN
0
T is high. However, even though n-type field effect transistor TN
0
T is turned on, fuse F
0
T prevents the discharge path formed by n-type field effect transistor TN
0
T and fuse F
0
T from being enabled. Likewise, if the stored defective address has an address A
0
that is a logic zero, fuse F
0
N is blown or opened. Thus, when received address A
0
is low, complementary address A
0
T is high. However, even though n-type field effect transistor A
0
N is turned on, fuse F
0
N prevents the discharge path formed by n-type field effect transistor TN
0
N and fuse F
0
N from being enabled. Other stored addresses are similarly programmed so that when there is a match between the applied address (A
0
to An) and the stored address, all discharge paths are disabled and internal node ND remains high.
Buffer BF
700
receives internal node ND and provides a coincidence detection signal RE.
The operation of the first conventional example illustrated in
FIG. 9
will now be described.
First, a defect address is determined by a probe test. Fuses (F
0
T-F
0
N to FnT-FnN) are selectively cut or blown in accordance with the defect address to provide a stored defect address in the coincidence detecting circuit
700
A. For example, when the least significant bit of the defect address is a logic one, fuse F
0
T, of the pair of fuses (F
0
T and F
0
N) that correspond to external address A
0
, is blown or cut. In this way, fuse F
0
T that forms the discharge path when the true address A
0
T is high is cut and fuse F
0
N that forms the discharge path when the complementary address A
0
T is high is left intact. Respective fuse pairs (F
1
T-F
1
N to FnT-FnN) are programmed in accordance with other logic values of the defect address.
As described above, the stored defect address is programmed in the coincidence detecting circuit
700
A. During operation, the stored defect address is compared with the receive address (A
0
to An) every time the received address (A
0
to An) changes value. In other words, for example, if the external address A
0
changes from a logic zero to a logic one, address transition detecting circuit
700
B detects the change (transition) and outputs a low level pulse as the reset signal &phgr;r. Upon receiving the reset signal &phgr;r, the p-type field effect transistor TP
700
in coincidence detecting circuit
700
A is temporarily turned on to charge (precharge) the parasitic capacitance of the internal node ND to a high level.
When the address A
0
changes to a logic one, true address A
0
T becomes high and n-type field effect transistor TN
0
T is turned on. However, because fuse F
0
T is in the cut state, the discharge path formed by n-type field effect transistor TN
0
T and fuse F
0
T does not conduct current. Because address A
0
is low, complementary address A
0
T remains low and n-type field effect transistor TN
0
N is turned o

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