Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-05-28

2004-03-30

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S148000, C365S188000

Reexamination Certificate

active

06714439

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-159944, filed on May 29, 2001; the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of Related Art
Generally, one of the effective methods of reducing the power consumption of a semiconductor integrated circuit including MOSFET's, particularly the power consumption of a CMOS integrated circuit, is to decrease a driving voltage. If the driving voltage is decreased, however, the operating speed of the CMOS circuit is reduced. If not only the driving voltage but also a threshold voltage is decreased, it is possible to reduce the power consumption of the circuit in operation without reducing the operating speed thereof. If the threshold is decreased, however, the sub-threshold current of each MOSFET increases and the power consumption of the circuit in a standby state thereby increases. Particularly, in a semiconductor memory device, if the driving voltage thereof is to be decreased, such disadvantages as the decrease of a gain in an operating range of a CMOS device which constitutes a memory cell, the increase of a stand-by current following the decrease of the threshold Vth of each MOSFET occur. To avoid these disadvantages, there is proposed the use of DTMOS's (Dynamic Threshold voltage MOSFET's) each having a gate connected to a substrate, as MOSFET's which constitute a memory cell. If the DTMOS's are used, it is possible to decrease a stand-by current and to obtain a large gain at a low driving voltage. It is, therefore, possible to configure a circuit which can stably operate at high speed.
The configuration and layout of a conventional memory cell which uses CMOS devices as constituent elements are shown in
FIGS. 8 and 9
, respectively. The configuration and layout of a conventional memory cell which uses DTMOS's as constituent elements are shown in
FIGS. 10 and 11
, respectively.
In
FIG. 8
, a memory cell
70
includes two transfer gates
72
and
73
, and a data storage section
80
. The data storage section
80
includes a CMOS inverter
83
which consists of a p channel MOSFET
81
and an n channel MOSFET
82
, and a CMOS inverter
86
which consists of a p channel MOSFET
84
and an n channel MOSFET
85
. The input terminal of the CMOS inverter
83
is connected to the output terminal of the CMOS inverter
86
. The output terminal of the CMOS inverter
83
is connected to the input terminal of the CMOS inverter
86
. Therefore, the CMOS inverters
83
and
86
constitute a cross-connection configuration. Each of the transfer gates
72
and
73
consists of an n channel MOSFET and the gate thereof is connected to a word line WL.
In addition, the drain of the transfer gate
72
is connected to a bit line BL and the source thereof is connected to the output terminal of the CMOS inverter
83
, i.e., the drains of the MOSFET's
81
and
82
. The drain of the transfer gate
73
is connected to a bit line/BL and the source thereof is connected to the output terminal of the CMOS inverter
86
, i.e., the drains of the MOSFET's
84
and
85
. Further, a well or a substrate in which the transfer gates
72
and
73
are formed is connected to the sources of the MOSFET's
82
and
85
.
In the memory cell
70
constituted as stated above, the transfer gates
72
and
73
and the n channel MOSFET's
82
and
85
are formed in the same well
101
and the p channel MOSFET's
81
and
84
are formed in the same well
102
as shown in FIG.
9
. The gates of the transfer gates
72
and
73
are configured as the word line WL of, for example, polysilicon. A diffused layer
72
b
which becomes the drain of the transfer gate
72
is connected to the bit line BL and a diffused layer
72
a
which becomes the source of the transfer gate
72
, becomes the drain of the MOSFET
82
. A diffused layer
73
b
which becomes the drain of the transfer gate
73
is connected to the bit line/BL and a diffused layer
73
a
which becomes the source of the transfer gate
73
, becomes the drain of the MOSFET
85
. Diffused layers
82
a
and
85
a
which become the sources of the MOSFET's
82
and
85
are connected to the well
101
and a ground power supply by wirings, respectively.
Further, the gates of the MOSFET's
81
and
82
are configured as a wiring
105
of, for example, polysilicon. This wiring
105
is connected to diffused layers
84
b
and
73
a
which become the drains of the MOSFET's
84
and
85
, respectively. The gates of the MOSFET's
84
and
85
are constituted as a wiring
106
made of, for example, polysilicon. This wiring
106
is connected to diffused layers
81
b
and
72
a
which become the drains of the MOSFET's
81
and
82
, respectively. Diffused layers
81
a
and
84
a
which become the sources of the MOSFET's
81
and
84
, respectively, are connected to the well
102
and a driving power supply.
Meanwhile, as shown in
FIG. 10
, the conventional memory cell which uses DTMOS's includes two transfer gates
76
and
77
, and a data storage section
90
. The data storage section
90
includes a CMOS inverter
93
which consists of a p channel MOSFET
91
and an n channel MOSFET
92
, and a CMOS inverter
96
which consists of a p channel MOSFET
94
and an n channel MOSFET
95
. The input terminal of the CMOS inverter
93
is connected to the output terminal of the CMOS inverter
96
. The output terminal of the CMOS inverter
93
is connected to the input terminal of the CMOS inverter
96
. In addition, the potential of the input terminal of the CMOS inverter
93
is applied as the substrate bias of the CMOS inverter
93
. The potential of the input terminal of the CMOS inverter
96
is applied as the substrate bias of the CMOS inverter
96
.
Each of the transfer gates
76
and
77
consists of an n channel MOSFET and the gate thereof is connected to a word line WL. The drain of the transfer gate
76
is connected to a bit line BL, and the source thereof is connected to the output terminal of the CMOS inverter
93
, i.e., the drains of the MOSFET's
91
and
92
. The drain of the transfer gate
77
is connected to a bit line/BL, and the source thereof is connected to the output terminal of the CMOS inverter
96
, i.e., the drains of the MOSFET's
94
and
95
. A well or a substrate in which the transfer gate
76
is formed is connected to the gate of the transfer gate
76
or the substrate. A well or a substrate in which the transfer gate
77
is formed is connected to the gate of the transfer gate
77
or the substrate.
In the memory cell
90
constituted as stated above, as shown in
FIG. 11
, the transfer gates
76
and
77
, the n channel MOSFET's
92
and
95
, and the p channel MOSFET's
91
and
94
are formed in different wells. Namely, the transfer gate
76
is formed in a well
111
, the transfer gate
77
is formed in a well
112
, the MOSFET
92
is formed in a well
113
, the MOSFET
95
is formed in a well
114
, the MOSFET
91
is formed in a well
115
, and the MOSFET
94
is formed in a well
116
.
The gates of the transfer gates
76
and
77
are configured as a word line WL of, for example, polysilicon. In addition, a diffused layer
76
b
which becomes the drain of the transfer gate
76
, is connected to the bit line BL. A diffused layer
76
a
which becomes the source of the transfer gate
76
is connected to diffused layers
91
b
and
92
b
which become the drains of the MOSFET's
91
and
92
, respectively, and also connected to a wiring
122
of, for example, polysilicon which becomes the gates of the MOSFET's
94
and
95
. A diffused layer
77
b
which becomes the drain of the transfer gate
77
is connected to a bit line/BL. A diffused layer
77
a
which becomes the source of the transfer gate
77
is connected to diffused layers

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