Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2002-06-24
2004-05-04
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S230060, C365S230080, C365S233100
Reexamination Certificate
active
06731549
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, such as, for example, an SRAM (static random access memory).
2. Description of the Related Art
Most recent semiconductor integrated circuits receive an input signal through an input end thereof in an asynchronous state which does not depend on a clock signal, and execute an operation in response to the input signal at a relatively high frequency on the order of several tens of megahertz. A known example of such a semiconductor device is a semiconductor memory device referred to as an SRAM.
An SRAM includes a plurality of memory cells. The SRAM receives an address signal through an address end thereof and statically accesses a memory cell corresponding to the value of the received address signal so as to perform a read or write operation. Such an operation of the SRAM does not depend on a clock signal which indicates that the value of the address signal input to the address end is valid. Therefore, the read or write operation can be performed rapidly in response to the input address signal.
In the SRAM having the above-described structure, the timing at which the address signal is supplied may widely vary. In one example, after a series of address signals are supplied sequentially from the address end to the SRAM at a high speed of, for example, 20 MHz, a state of the signal which is input from the address end does not change for a relatively long time period. In a conventional SRAM in which a memory cell is accessed completely statically, the access to the memory cell selected in accordance with the value of the address signal supplied to the address end is maintained during the time period in which the state of the address signal does not change, unless the SRAM is controlled by another method using, for example, a chip select signal or an output enable signal.
In order to reduce an amount of power required for the relatively long time period in which the value of the address signal does not change (hereinafter, referred to as a “timeout period”) and improve an internal dynamic operating performance, most of the recent SRAMs include an address transition detection (ATD) circuit.
The ATD circuit detects a state transition of the signal which is input to an input end, especially an address end, of the SRAM, and generates an internal control signal in response to the detection of the state transition. The SRAM uses the ATD circuit in order to generate the internal control signal after the state transition of the address signal supplied to the SRAM is detected and before an address decoder accesses a desired memory cell. Thus, the SRAM can perform an internal operation such as, for example, a pre-charging operation of a bit line, and activation and deactivation of a sense amplifier. Such an internal operation may alternatively be performed after a prescribed timeout period passes in a cycle in which a memory cell is accessed (access cycle). When a new address signal is supplied to the SRAM, the ATD circuit detects a state transition of the address signal which is input to the address end and generates an internal control signal. Thus, the components of the SRAM which are necessary for the internal operations are activated, and a memory cell corresponding to the value of the new address signal is accessed.
When an address signal including a state transition at, for example, a high frequency is supplied to an SRAM or the like including the ATD circuit, a plurality of word lines in a memory array are undesirably selected and activated simultaneously regardless of whether the state transition is performed intentionally or occurs due to noise. This may undesirably result in that data stored in a memory cell of the SRAM is destroyed or a high level of current causes damage in the SRAM. In order to prevent the plurality of word lines from being simultaneously activated, it has been proposed that all the word lines be forcibly placed into an of f state (inactive state) during a time period in which the operation is in an equilibrium state in, for example, a second half of the access cycle. However, this conventional technique involves an undesirable possibility that a state transition of the address signal occurs before all the word lines are forcibly placed into the off state in the case where an input buffer circuit, provided for buffering the address signal supplied to the SRAM or other types of semiconductor memory devices, has a sufficiently high response speed. Therefore, this technique is not effective for preventing the plurality of the word lines from being simultaneously activated.
In order to solve these problems, Japanese Laid-Open Publication No. 6-176575, for example, discloses an input buffer circuit as shown in FIG.
4
. The input buffer circuit shown in
FIG. 4
is provided to each address end for receiving an address signal supplied to the SRAM or other types of semiconductor memory devices. The input buffer circuit includes an input stage
110
, a delay circuit
116
, a bus gate
118
, an ATD circuit
120
, and a latch
130
.
The input stage
110
includes a terminal A for receiving an address signal, a terminal CE_ for receiving a chip enable signal, two P-channel pull-up transistors
112
a
and
112
b
, and two N-channel pull-down transistors
114
a
and
114
b
. A gate of one of the P-channel pull-up transistors
112
a
and a gate of one of the N-channel pull-down transistors
114
a
receive an address signal A
1
(
FIG. 5
) from the terminal A. A gate of the other P-channel pull-up transistor
112
b
and a gate of the other N-channel pull-down transistor
114
b
receive a chip enable signal from the terminal CE_. An output end of the input stage
110
is connected to the delay circuit
116
and the ATD circuit
120
via inverters
113
and
115
. The delay circuit
116
and the ATD circuit
120
each receive a signal B_ (
FIG. 5
) which is obtained by inverting the logic level of the address signal A
1
.
The delay circuit
116
outputs the signal B_ after a prescribed delay time period. An output end of the delay circuit
116
is connected to the bus gate
118
via an inverter
117
, and the bus gate
118
receives a signal AD (
FIG. 5
) which is obtained by inverting the logic level of the signal B_ with a prescribed delay time period.
The ATD circuit
120
includes a delay gate
124
a
for directly receiving the signal B_ and a delay gate
124
b
for receiving the signal B_ via an inverter
123
. The signal output from the delay gate
124
a
is input to one of two input terminals of a delay gate
126
a
. The signal output from the delay gate
126
a
is input to one of two input terminals of a delay gate
126
b
. The signal output from the delay gate
126
b
is input to one of two input terminals of a delay gate
126
c
. The other input end of the delay gate
126
a
, the other input end of the delay gate
126
b
, and the other input end of the delay gate
126
c
each receive the signal B_ via the inverter
123
and another inverter
125
.
The signal output from the delay gate
126
c
via an inverter
129
a
(signal BD) is sent to one of two input terminals of a NAND gate
122
a
. As shown in
FIG. 5
, the signal BD is obtained by inverting the logic level of the signal B_. Specifically, a starting point of a pulse (falling edge) of the signal BD is delayed with respect to a starting point of a pulse (rising edge) of the signal B_ by a time period t
d
.
Returning to
FIG. 4
, the other input end of the NAND gate
122
a
receives the signal B_ which is input to the ATD circuit
120
. The signal output from the NAND gate
122
a
(signal P_) is sent to one of two input terminals of a NAND gate
128
. As shown in
FIG. 5
, the signal P_ is kept in an inactive state for the time period t
d
when both the signals B_ and BD are in an active state.
Referring to
FIG. 4
, the signal output from the delay gate
124
b
is input to one of two input terminals of a delay gate
126
d
. The signal output from the delay gate
126
d
is input to one of two input ter
Ho Hoai
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
Tran Long
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