Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-05-15

2004-04-13

Tran, Michael (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S236000

Reexamination Certificate

active

06721223

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, to a semiconductor memory device requiring refresh of storage data. More particularly, the present invention relates to a configuration for reducing a current consumption in a low power consumption mode such as a sleep mode.
2. Description of the Background Art
As one of semiconductor memory devices, there is a DRAM (dynamic random access memory). In DRAM, a memory cell is usually constituted of one capacitor and one MIS transistor (an insulated gate field effect transistor). This memory cell is smaller in occupancy area of a memory cell and lower in cost per bit, as compared with a memory cell of an SRAM (static random access memory) in which a memory cell of one bit is constituted of 4 transistors and two load elements. For the reasons, DRAMs have been widely used as memory devices with a large storage capacity.
DRAM stores data in a capacitor in the form of an electric charge, and therefore, there is a possibility that stored data is lost by a leakage current and others. Therefore, refreshing operations of restoring the storage data regularly is needed.
An operating mode of performing refresh usually includes an auto-refresh mode and a self-refresh mode. In the auto-refresh mode employed in a normal operation mode, that is, in an operating mode in which data access is made to DRAM, and the external access is ceased for externally applying a refresh instruction (an auto-refresh command). Inside DRAM, a refresh address and a refresh control signal are generated according to the auto-refresh command for executing refresh of stored data.
The self-refresh mode is set by a self-refresh instruction (a self-refresh command) applied externally in a low power consumption mode such as a sleep mode, in which no access to DRAM continues for a long period of time. In the self-refresh mode, DRAM generates a refresh timing and a refresh address internally to execute refresh of memory cell data at prescribed intervals. The self-refresh mode is set in the low power consumption mode and a current consumption in the self-refresh mode is required to be as low as possible.
In a conventional DRAM, in the self-refresh mode, refresh is also performed in the same control manner as in the refresh executed in the auto-refresh mode. For example, in a 4 bank configuration, the 4 banks are refreshed in any of the auto-refresh mode and the self-refresh mode, and the number of rows of memory cells refreshed is set to two in any bank in both refresh modes.
The auto-refresh mode is a refresh mode to be executed in the normal operation mode in which data processing is performed and a low current consumption is not so required, dissimilarly to the low power consumption mode such as the sleep mode. On the other hand, in the low power consumption mode, the current consumption is required to be as low as possible. Therefore, in a conventional configuration, a problem arose that in the low power consumption mode, a required condition for a current consumption cannot be met. Especially, in applications for battery-powered portable equipment and such, only data holding is required in such a low power consumption mode and the current consumption is further required to be as low as possible from the view point of a longer battery lifetime. Accordingly, in the conventional refresh scheme, there arose a problem that such a requirement for a low current consumption could not be met.
Furthermore, a refresh cycle (the number of times of refresh performed for refreshing all memory cells once) is, for example, a 4 K refresh cycle, an 8 K refresh cycle or the like, and the refresh cycle is fixedly set by a bonding option of setting a specific pad at a prescribed voltage level with a bonding wire. Therefore, if an operating environment changes, or a data holding characteristic of a memory cell is deteriorated due to rise in operating temperature or other reasons, a possibility arises that storage data could not be stably held within a set refresh cycle.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device capable of reducing a current consumption in a low power consumption mode.
It is another object of the present invention to provide a semiconductor memory device capable of reducing a current consumption in execution of self-refresh in a self-refresh mode
It is still another object of the present invention to provide a semiconductor memory device capable of reducing a current consumption in refresh without deteriorating a data holding characteristic.
It is a further object of the present invention to provide a semiconductor memory device capable of changing a refresh execution fashion with ease according to an operation environment.
A semiconductor memory device according to a first aspect of the present invention includes: a memory array having a plurality of memory cells; a refresh circuit for refreshing storage data of a memory cell in the memory array; and a register circuit for storing data setting at least one of a refresh cycle and a refresh region of the memory array. The register circuit stores externally applied refresh specifying data in response to an externally applied register set instruction signal.
The semiconductor memory device according to the first aspect of the present invention further includes: a refresh execution control circuit for generating a refresh address specifying a memory cell to be refreshed in the memory array for applying the generated refresh address to the refresh circuit and to activate the refresh circuit according to data stored in the register circuit.
The refresh specifying data preferably includes data specifying a region of a refresh target in the memory array.
A semiconductor memory device according to a second aspect of the present invention includes: a plurality of banks each having a plurality of memory cells arranged in rows and columns, and each driven to a selected state independently from the other (s); and a refresh address generation circuit for generating a refresh address for refreshing memory cells in the plurality of banks in a refresh operation. The refresh address generation circuit includes a circuit for generating a refresh bank address specifying a bank in the plurality of banks. The refresh bank address specifies some of the plurality of banks in a low power consumption mode, while specifying all of the plurality of banks in a mode different from the low power consumption mode.
The semiconductor memory device according to the second aspect of the present invention further includes: a refresh execution control circuit for executing refresh of a memory cell in a bank specified by the refresh address from the refresh address generation circuit in the refresh operation.
By setting contents of a refresh operation executed in the low power consumption mode according to stored data in the mode register, a current consumed in refreshing in the low power consumption mode can be reduced, as compared with that in a refresh operation executed in the normal operation mode. Furthermore, by setting contents of a refresh operation using the mode register, the contents of a refresh operation can be set according to an application to enable a changing/setting of the contents of execution of refresh adaptably to an operation environment flexibly.
Furthermore, in a multi-bank configuration, by reducing the number of banks simultaneously activated in refresh, further reduction can be ensured in current consumption for refresh executed in the low power consumption mode in which data holding is performed, as compared with refresh executed in the normal operation mode.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 6215714 (2001-04-01), Takemae et al.
patent: 61-212116 (1986-09-01), None

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