Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-10-11

2004-03-02

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233500, C365S233100, C365S194000, C365S236000, C365S230080, C365S230030

Reexamination Certificate

active

06700828

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to setting of a pulse width of an address transition signal in a semiconductor memory device.
2. Description of the Related Art
Typical examples of the semiconductor memory device include a DRAM and an SRAM. As is well known, the DRAM is more affordable in price and has a larger capacity than the SRAM, but requires the refreshing operation. The SRAM does not require any refreshing operation and is easily handled, but is more expensive and has a smaller capacity than the DRAM.
A virtual SRAM (called VSRAM or PSRAM) is known as a semiconductor memory device having the advantages of the DRAM and the SRAM. The virtual SRAM has a memory cell array of dynamic memory cells like the DRAM, and includes a refresh controller to perform the internal refreshing operation. An external device (for example, a CPU) connecting with the virtual SRAM can thus gain access to the virtual SRAM (for reading or writing data) without being specifically conscious of the refreshing operation. This characteristic of the virtual SRAM is referred to as ‘permeability of refresh’.
Some virtual SRAMs do not require input of an external clock signal. Such a virtual SRAM includes an address transition detection circuit, which detects a variation of an address supplied from an external device (for example, a CPU) by at least one bit and generates an address transition signal based on a result of the detection. Namely the address transition signal is used instead of the external clock signal. The external device (for example, the CPU) gains access to the virtual SRAM with the address transition detection circuit by the same procedure as that for accessing a conventional asynchronous SRAM.
In the description below, the address transition detection circuit may be referred to as the ‘ATD circuit’, and the address transition signal may be referred to as the ‘ATD signal’.
The address supplied from the external device (for example, the CPU) to the virtual SRAM is generally transmitted in parallel by means of multiple (for example, 20) signal lines. Each signal line corresponds to one bit. In the case of a variation in address from a certain value to another value, it is preferable to simultaneously change all the bits involved in the address variation among the respective bits transmitted via the multiple signal lines.
When all the bits involved in the address variation are changed simultaneously, the ATD circuit included in the virtual SRAM accurately detects the address variation and ensures generation of an appropriate ATD signal.
In the actual state, however, a variation of the circuit elements or a variation of the signal lines causes a phase difference or a timing difference among the bits. The respective bits involved in the address variation may thus be changed at deviated timings. Such deviation of the timing is generally called an address skew.
In the prior art technique, the ATD circuit may not accurately detect the address variation nor generate the appropriate ATD signal under the condition of occurrence of an address skew.
FIG. 20
is a timing chart showing a variation in level of the ATD signal and external access executed in response to the ATD signal in the case of occurrence of an address skew in the prior art technique.
The address supplied to the virtual SRAM is 20-bit data of A
0
through A
19
. The bits A
0
through A
9
are changed as shown in FIG.
20
(
a
), the bit A
10
is changed as shown in FIG.
20
(
b
), and the bits A
11
through A
19
are changed as shown in FIG.
20
(
c
). In this example, the bits other than the bit A
10
are changed at a time point t1, whereas the bit A
10
is changed at a later time point t2. Namely the timing of the change of the bit A
10
is deviated from the timing of the change of the other bits. This causes an address skew.
In the case of the occurrence of the address skew, the ATD circuit detects a change of the bits other than the bit A
10
at the time point t1 and makes the ATD signal rise to have a pulse of a fixed width as shown in FIG.
20
(
d
). The ATD circuit then detects a change of the bit A
10
at the time point t2 and makes the ATD signal rise again to have another pulse of the fixed width.
While it is expected that the ATD signal rises to have one pulse in response to detection of the address variation, the prior art technique makes the ATD signal rise to have two pulses within a short time. This prevents generation of the appropriate ATD signal.
As described above, the ATD signal is used in place of the external clock signal in the virtual SRAM and represents a reference timing of external access to the memory cell array or a refreshing operation of the memory cell array. More specifically, the refreshing operation starts based on the timing of a rise of the ATD signal, whereas the external access starts in principle based on the timing of a rise of the ATD signal.
The hindrance of generation of the appropriate ATD signal causes malfunctions of the external access and the refreshing operation. In the worst case, destruction of data may occur in part of the memory cells included in the memory cell array.
The longer pulse width of the ATD signal leads to the longer access time as discussed later. The prior art technique thus sets the pulse width of the ATD signal to several nsec, which ensures absorption of noise.
SUMMARY OF THE INVENTION
The object of the present invention is thus to provide a semiconductor memory device that generates an appropriate address transition signal even in the case of occurrence of an address skew in an externally given address.
In order to attain at least part of the above and the other related objects, the present invention is directed to a first semiconductor memory device, which includes: a memory cell array of dynamic memory cells; an address transition detection module that detects a variation of an externally given address by at least one bit and generates an address transition detection signal, which shifts to a second state in response to detection of the variation of the address in a first state and re-shifts to the first state when a preset reference time period elapses since the shift to the second state; a refresh control module that starts a refreshing operation of a desired memory cell included in the memory cell array, based on a timing of the shift of the address transition detection signal from the first state to the second state; and an external access control module that starts an external access to a memory cell in the memory cell array specified by the externally given address, based on a timing of the re-shift of the address transition detection signal from the second state to the first state or a timing of conclusion of the refreshing operation. The reference time period is set to be not shorter than a preset allowable address skew range with regard to the address and not to be longer than a time period between the shift of the address transition detection signal to the second state and the conclusion of the refreshing operation.
In the first semiconductor memory device of the present invention, the refreshing operation starts, based on the timing of the shift of the address transition detection signal from the first state to the second state. The external access starts, based on the timing of the re-shift of the address transition detection signal from the second state to the first state or the timing of conclusion of the refreshing operation. The allowable address skew range is set in advance. On these premises, the reference time period of the address transition detection signal is set to be not shorter than the preset allowable address skew range and not to be longer than the time period between the shift of the address transition detection signal to the second state and the conclusion of the refreshing operation. Here the reference time period of the address transition detection signal denotes the time period between the timing of the shift from the first state to the second state and the timing of the re-shif

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