Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2003-02-05

2004-03-02

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S368000

Reexamination Certificate

active

06700169

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device. More specifically, the present invention relates to arrangement of sense amplifier (SA) driver transistors driving sense amplifiers.
2. Description of the Prior Art
In recent years, high-speed operation of a consolidated DRAM equipped with a DRAM (Dynamic Random Access Memory) and a logic IC has been required and developed.
To realize the high-speed operation, non-shared type sense amplifiers are employed in a DRAM part in place of shared type sense amplifiers widely used in a general-purpose DRAM. In addition, sense amplifier driver transistors are distributed in sense amplifier arrays. The size of a sense amplifier region is increased. Reduction in size of the sense amplifier region is a new problem. It is essential to reduce the size of the sense amplifier region in order to reduce the manufacturing cost.
As a method for reducing the size of the sense amplifier region, the layout of the sense amplifier region shown in
FIG. 18
is provided. In the layout, the size of a sense amplifier circuit
11
of the sense amplifier circuit
11
and a sense amplifier driver transistor
15
forming a sense amplifier region
2
is reduced.
The method contrives the shape of gates G of sense amplifier transistors (pair sense amplifier transistors
14
) connected to one or more complementary bit lines (BT
1
to BTm, BN
1
to BNm) connected to a memory cell array. The shape of the gates G is U shaped on a diffusion layer region L forming sources S and drains D. Such shape can share the diffusion layer region L forming the sources S of the sense amplifier transistors to form the sense amplifier transistors. The gates G of the sense amplifier transistors can be formed on the same diffusion layer region L. The size of the sense amplifier circuit
11
can be reduced.
In the arrangement, the sense amplifier driver transistor
15
driving the sense amplifier transistors is arranged adjacent the sense amplifier circuit
11
in the bit line direction.
The length of the sense amplifier driver transistor
15
in the bit direction is about 1.0 &mgr;m. In N- and P-channels for one sense amplifier circuit, &Dgr;L≈2.0 &mgr;m. The size of the sense amplifier driver transistor
15
of the semiconduct or memory device in the bit line direction is expressed by 2.0 &mgr;m×the number of sense amplifier arrays. For example, in the case of 64 sense amplifier arrays, L=2.0 &mgr;m×64=128 &mgr;m (approximately).
A method for reducing the size of the sense amplifier driver transistor
15
is described in Japanese Patent Application Laid-Open No. 2000-124415. Its summary describes “having sense amplifiers including a pair of N channel MOS transistors and a pair of P channel MOS transistors connected to complementary bit lines of a memory cell array; and driver MOS transistors driving the sense amplifiers and distributed in the sense amplifiers, wherein the gates of the pair of N channel MOS transistors and the pair of P channel MOS transistors are U shaped on a diffusion layer, and the N- and P-channel side driver MOS transistors are arranged between the pair of N channel MOS transistors and the pair of P channel MOS transistors, respectively, so as to share the diffusion layer.”
Japanese Patent Application Laid-Open No. 2000-124415 describes “Since the N- and P-channel sense amplifier MOS transistors and the sense amplifier driver MOS transistors share the diffusion layer, an increase in area of the sense amplifier part can be minimized.”
The method for reducing the area of the sense amplifier region
2
has the following problem.
In Japanese Patent Application Laid-Open No. 2000-124415, as shown in
FIG. 19
, the sense amplifier driver circuit
15
is formed between the sense amplifier transistors of the pair sense amplifier transistors
14
forming the sense amplifier circuit
11
. The source S and the drain D of the sense amplifier driver transistor
15
are formed to share the diffusion layer L forming the source S and the drain D of the sense amplifier transistors
14
. This can prevent the size from being increased in the bit line direction.
FIG. 19
is the same as
FIG. 18
in that the sense amplifier driver transistor
15
is arranged in the proximity of the sense amplifier circuit
11
. The sense amplifier size is inevitably increased in the bit line direction by the sense amplifier driver transistor
15
.
BRIEF SUMMARY OF THE INVENTION
3. Summary of the Invention
A semiconductor memory device of the present invention having sense amplifier transistors connected to complementary bit lines of a memory cell array and sense amplifier driver transistors driving the sense amplifier transistors, wherein the sense amplifier transistors and the sense amplifier driver transistors have gate electrodes dividing a common diffusion layer region formed on the surface of a semiconductor substrate into two, respectively, the gate electrodes being arranged on the boundary of the diffusion layer region.


REFERENCES:
patent: 2003/0151085 (2003-08-01), Kuroki
patent: 2000-124415 (2000-04-01), None

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