Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-11-06

2003-11-11

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C257S071000

Reexamination Certificate

active

06646907

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly relates to a semiconductor memory device including memory cells, which have specific or distinctive structures, as well as a semiconductor memory device having a memory cell array, which has a specific or distinctive structure.
2. Description of the Background Art
A memory cell of one-transistor and one-capacitor structure is liable to loose its information, and particularly, data at a high potential level (H-data) due to leak of electric charges stored in the capacitor. In recent years, such a method has been proposed that uses two memory cells for writing H-data and L-data (i.e., data at a lower potential than H-data) therein, respectively. This method is devised to utilize a difference in amount of stored electric charges between the two memory cells, and thereby provide a Dynamic Random Access Memory (DRAM) performing a larger operation.
However, the above method requires two transistors and two capacitors, and therefore suffers from such a problem that areas of the memory cells are large. Accordingly, it has been desired to develop a semiconductor memory device, which does not occupy a large area, and can hold data with high stability.
SUMMARY OF THE INVENTION
An object of the invention is to provide a semiconductor memory device using memory cells, which have structures not increasing areas, and are arranged in a distinctive manner providing high data holding stability.
According to a first aspect of the invention, a semiconductor memory device includes memory cells formed on a main surface of a semiconductor substrate and each having first and second transistors each having a gate electrode and impurity regions forming source/drain as well as one capacitor, and bit and word lines for controlling an operation of the memory cells. In this semiconductor memory device, a cell plate of the capacitor is formed of the same layer as the gate electrode.
According to this structure, the memory cell can have the structure including the two transistors, which are arranged on the cell plate side and the storage node side with the one capacitor therebetween, respectively. Therefore, the memory cell having high signal holding stability can be formed by devising control. Since the memory cell employs only one capacitor, the memory cell occupies only a small area.
According to the structure described above, the cell plate and the gate electrode can be formed of the same interconnection layers. Therefore, formation of the memory cell structure including the memory cell capacitor and formation of the transistors can be performed in parallel with each other within the same manufacturing steps, and therefore, the manufacturing steps can be simplified. The “same interconnection layers” described above mean the interconnection layers arranged at the same level, having the same thickness and made of the same material. The semiconductor memory device according to the invention may be a DRAM, an ERAM and others. This is true also with respect to semiconductor memory devices, which will be described later.
In the semiconductor memory device of the first aspect, the cell plate may be in electrical communication with the impurity region of the first transistor, and may be opposed to the impurity region of the second transistor with a dielectric layer therebetween.
Owing to the above structure, the memory cell can have the capacitor arranged between the two transistors. The impurity regions described above may include an impurity region, which is enlarged and deformed as compared with an impurity region of a normal transistor for increasing the capacitance of the capacitor.
The semiconductor memory device of the first aspect may have an interconnection layer located at the same level as the bit line. The interconnection layer may have a side connected to the impurity region of the first transistor via a first plug interconnection as well as another side connected to the cell plate via a second plug interconnection.
According to this structure, an interconnection for connection between the cell plate and the first transistor can be arranged within a space between the bit lines. As a result, the interconnection layer can be simple.
The semiconductor memory device of the first aspect may include a plug interconnection overlapping, in a plan view, with a side edge of the cell plate and a side edge of the impurity region of the first transistor. A portion of the plug interconnection overlapping with the side edge of the cell plate may be in contact with the cell plate, and a portion of the plug interconnection overlapping with the impurity region of the first transistor may be in contact with the impurity region of the first transistor.
Owing to the above structure, only one plug interconnection is required for establishing the foregoing connection. Therefore, the connection between the impurity region of the first transistor and the cell plate can be achieved by an extremely simple structure. The bit line is merely required to avoid the upper end of the plug interconnection. This increases the flexibility in planar arrangement of the bit line. For example, all the bit lines can be arranged linearly. Therefore, the layout of the bit line can be simple.
The semiconductor memory device according to the first aspect may include an insulating layer at a level lower than the impurity regions of the first and second transistors for interrupting conduction between the impurity regions and its lower side.
This structure can effectively prevent leak of electric charges from the memory capacitor. The insulating layer may be formed by implanting oxygen ions. Alternatively, a substrate such as an SOI (Substrate on Insulator) provided with an insulating layer, which is located under a semiconductor layer, may be used so that the insulating layer may function as a layer for preventing leak of electric charges.
In the semiconductor memory device of the first aspect, an impurity concentration of the impurity region of the second transistor opposed to the cell plate may be higher than that of the other impurity region of the second transistor.
This structure can improve a capacity efficiency of an MOS capacity formed of the cell plate. The other impurity region described above is the impurity region spaced from the impurity region, which is opposed to the cell plate, with the channel region therebetween.
A semiconductor memory device according to a second aspect of the invention includes memory cells formed on a main surface of a semiconductor substrate and each having first and second transistors each having a gate electrode and impurity regions forming source/drain as well as one capacitor, and bit and word lines for controlling an operation of the memory cells. In this semiconductor memory device, a cell plate forming an electrode of the capacitor has a belt-like form extending along the word line, and the impurity regions of the first and second transistors are opposed to the cell plate, are continuous to each other and are located along the belt-like cell plate.
When arranging the memory cells in the array, connection is made in such a fashion that the impurity regions of the memory cells in each unit are opposed to the common cell plate. Therefore, when effecting exposure on the silicon substrate for forming the impurity regions of the memory cells, it is not necessary to space the individual impurity regions from each other, and the impurity regions can be continuous to each other. Therefore, the exposing margin can be remarkably large, and the yield can be significantly improved.
In the semiconductor memory device of the second aspect, the cell plate may be located as a layer at the same level as the gate electrode serving also as the word line.
According to this structure, the cell plate and the gate electrode can be formed of the same interconnection layer. Therefore, the memory cell including the memory cell capacitor can be formed substantially simultaneously with and thus in

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