Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-08-21

2003-02-11

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S203000, C365S207000

Reexamination Certificate

active

06519198

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-253888, filed Aug. 24, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly, to the high speed operation of a DRAM (Dynamic Random Access Memory).
2. Description of the Related Art
Various efforts have been made to data in an attempt to develop semiconductor memory devices such as DRAM having a high degree of integration and capable of achieving a high speed operation. On the other hand, the operation margin tends to be lowered because of the lowered power supply voltage caused by the progress of the fine process technology and because of the achievement of the high speed operation. The main reason for the difficulty is that it is difficult to lower the threshold voltage of the transistor in accordance with the lowered power supply voltage. Particularly, under an environment of a low power supply voltage, the operation margin of a circuit in which the wiring of a large capacitance is charged in a short time, e.g., a bit line sense circuit, tends to be lowered.
In order to overcome the problem, a bit line potential overdrive circuit for overdriving the potential of the bit line in charging the bit line has been used.
FIGS. 1A and 1B
collectively show the construction of the conventional bit line potential overdrive circuit.
FIG. 1A
shows the circuit construction of a DRAM, particularly, the memory region relating to the bit line potential overdrive circuit. The memory region of the DRAM shown in
FIG. 1A
comprises a memory cell array
10
formed by arranging memory cells in the form of a matrix, a row decoder
11
, a sense amplifier
12
arranged for column of the memory cell array, a bit line
5
and a complementary bit line
6
.
FIG. 1B
shows in a magnified fashion the circuit construction of the region denoted by an arrow in FIG.
1
A. To be more specific,
FIG. 1B
shows the typical circuit construction of each of a memory cell, a word line connected to the memory cell, a pair of bit lines, a sense amplifier for driving the bit lines, and an equalize circuit for equalizing the pair of bit lines.
The circuit shown in
FIG. 1B
comprises an equalize circuit formed of N-channel transistors Q
11
, Q
12
, Q
13
, a sense amplifier formed of P-channel transistors Q
1
n, Q
3
n and N-channel transistors Q
2
n, Q
4
n (n being a natural number), N-channel transistors Qs
1
, Qs
2
, a cell capacitor Cc, and a memory cell formed of a single cell transistor Qc.
Reference numerals
3
and
4
represent an NCS node and a PCS node, respectively. The voltage on the side of the P-channel transistor and the voltage on the side of the N-channel transistor each serving to activate the sense amplifier are applied to the NCS node
3
and the PCN node
4
, respectively. Reference numerals
5
and
6
represent a bit line BL and a complementary bit line /BL, respectively. Reference numeral
7
represents a signal line ISO for coupling the sense amplifier and the memory cell. Further, reference numeral
8
represents a word line WL. Incidentally, EQL represents an equalize signal line. If EQL is set at a high level, the potentials of the bit line BL and the complementary bit line /BL are set at VBLEQ, which is half the bit line final potential VBLH.
The conventional bit line potential overdrive circuit, which is directly relevant to the present invention, will now be described with reference to FIG.
2
.
The bit line potential overdrive circuit shown in
FIG. 2
comprises
0
-th to n-th sense amplifiers formed between the PCS node
3
and the NCS node
4
,
0
-th to n-th bit line pairs driven by these sense amplifiers, a P-channel transistor Q
5
serving to impart a bit line overdrive potential VINT to the PCS node upon receipt of a control signal /PSE
1
, a P-channel transistor Q
6
serving to impart a bit line final potential VBLH to the PCS node upon receipt of a control signal /PSET
2
, and an N-channel transistor Q
7
making the NCS node to the ground potential Vss upon receipt of a control signal NSET.
The operation of the conventional bit line potential overdrive circuit will now be described with reference to
FIG. 2
with attentions paid to the n-th sense amplifier and the bit line pair. The circuit construction of the n-th sense amplifier consisting of n-th P-channel transistors Q
1
n, Q
3
n and n-th N-channel transistors Q
2
n, Q
4
n is equal to that shown in FIG.
1
B.
AS shown in
FIG. 2
, in the n-th sense amplifier, the P-channel transistor Q
1
n and the N-channel transistor Q
2
n form a first complementary inverter, and the P-channel transistor Q
3
n and the N-channel transistor Q
4
n form a second complementary inverter.
The output of the first complementary inverter is connected to the input of the second complementary inverter via the complementary bit line /BL, and the output of the second complementary inverter is fed back to the first complementary inverter via the bit line BL so as to form a sense amplifier consisting of a complementary flip-flop.
The charge stored in the cell capacitor Cc having a miniature capacitance is amplified in the sense amplifier via the cell transistor Qc and the bit line of large wiring capacitance. Also, the stored memory data amplified by the sense amplifier is then restored in the cell capacitor Cc.
In order to rapidly amplify the charge stored in the cell capacitor Cc having a miniature capacitance via a large bit line capacitance, it is effective to add a bit line potential overdrive circuit serving to supply the charge required for changing the bit line in a short time to the sense amplifier.
The operation of the bit line potential overdrive circuit shown in
FIG. 2
will now be described more in detail with reference to
FIG. 3
showing the timing wave form diagram.
As described previously, power supplies of two systems supplying the bit line overdrive potential VINT and the bit line final potential VBLH (VBLH<VINT) are prepared for the PCS node of the conventional bit line potential overdrive circuit, and the bit line charging time is shortened by connecting the bit line to the power supply of the overdrive potential VINT higher than the final potential VBLH in the initial stage of the bit line charging.
FIG. 3
exemplifies the operation timing wave form of the bit line overdrive circuit. The operation of the conventional bit line overdrive circuit will now be described with reference to
FIG. 3
, where (1), (2) and (3) show respective time regions.
(1) Since each of /PSET
1
and /PSET
2
has a high level (hereinafter referred to as “H”), both Q
5
and Q
6
are in the off-state, NSET has a low level (hereinafter referred to as “L”), and Q
7
is in the off-state, the sense amplifier is under a stand-by (inactive) state and the potential of each of PCS and NCS is set at VBLH/2. Also, since the word line WLn is “L” and Qc is in the off-state, the cell capacitor Cc is separated from the bit line BLn.
(2) Since the states that /PSET
1
is “H”, /PSET
2
is “H”, and that NSET is “L” are left unchanged, the stand-by state of the sense amplifier is maintained. The word line WLn is set at “H” and the charge of the cell capacitor Cc is read on the bit line BLn.
(3) If NSET is set at “H” with each of /PSET
1
and /PSET
2
maintained at “H”, the transistor Q
7
is turned on so as to activate the N-channel side of the sense amplifier and lower the potential of the complementary bit line /BLn to Vss. Then, if the transistor Q
5
is turned on with /SET
1
set at “L”, the bit line BLn is connected to the power supply of the overdrive potential VINT so as to activate the P-channel side of the sense amplifier. It follows that the potential of the bit line BLn is rapidly elevated. If /PSET
1
is brought back to “H” so as to turn off the transistor Q
5
and, at the same time, /PSET
2
is set at “L” so as to turn off the transistor Q
6
before the poten

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