Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-06-28

2003-02-11

Elms, Richard (Department: 2829)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189050, C365S230060

Reexamination Certificate

active

06519199

ABSTRACT:

CROSS REFERENCES TO RELATED APPLICATIONS
This application claims priority from Korean Application, entitled “Semiconductor Memory Device” Application No. 2000-36407 , filed on Jun. 29, 2000 and incorporates by references its disclosure for all purposes.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device that prevents bit line separation signals from toggling, and, more particularly, to a semiconductor memory device that prevents bit line separation signals from toggling when word lines in the same block are enabled/disabled to, thereby reducing self-refresh current to minimize power consumption and improve the integrity of timing signals.
2. Prior Art of the Invention
FIG. 1
is a diagram showing conventional toggling of bit line separation signals (BISH/BISL). In conventional BISH/BISL toggling, BISH/BISL have three levels. The BISH/BISL an internal voltage level (VINT) when the word lines are not active (i.e., disabled), and the BISH/BISL corresponding to a selected block within an active bank have a power voltage level VPP and a ground voltage level VSS. When the word lines are disabled and thus not active, the BISH/BISL transitions to internal voltage VINT from either a level of VPP or VSS. When another block is active and its associated word lines are enabled, the BISH/BISL corresponding to that block transitions to power voltage VPP and ground voltage VSS. On the other hand, the BISH/BISL corresponding to unselected blocks (i.e., not active) remain steady at the internal voltage VINT level.
If the word lines are sequentially enabled, the corresponding BISH/BISL is toggled whenever one of the word lines is disabled, and current is consumed. Furthermore, since a conventional BISH/BISL driver drives the three levels, it burdens the complexity of the device design and layout. This is especially the case if such the conventional driver is disposed between sense amplifier blocks (i.e., within a cross area). The generation of the internal voltage VINT line also places a burden on the layout. As a result, the BISH/BISL load in conventional memories is too large, or too heavy, to effectively drive at the same time, which detrimentally affects tRCD (e.g., RAS to CAS DELAY TIME).
SUMMARY OF THE INVENTION
Therefore, the present invention provides a semiconductor memory device capable of reducing the self-refresh cycle current by preventing BISH/BISL toggling when word lines in the same block are enabled/disabled.
In accordance with an embodiment of the present invention, there is provided a semiconductor memory device having a cross area between a plurality of sense amplifier blocks, the memory device comprising: a self-refresh and internal address detector configured to receive a multiplicity of internal addresses and a self-refresh signal, for generating a signal determining whether bit line separation signals are to be toggled; a block selecting signal (MSI) latch for latching the output signal of the self-refresh and internal address detector and a block selecting signal; and a BISH/BISL controller receiving the output signals of the block-selecting signal latch to generate bit line separation signals, wherein the cross area between the sense amplifier blocks includes a bit line separation driver controlled by the bit line separation signals.


REFERENCES:
patent: 6246631 (2001-06-01), Park
patent: 6272631 (2001-08-01), Thomlinson et al.
patent: 6327204 (2001-12-01), Kook et al.

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