Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-09-20

2003-02-18

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000, C365S189040

Reexamination Certificate

active

06522569

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-284709, filed Sep. 20, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device using a ferroelectric film and, more particularly, to a highly integrated semiconductor memory device.
2. Description of the Related Art
A ferroelectric memory is advantageous because it is nonvolatile like a flash memory and is capable of not only a high-speed access and write like a DRAM but also low-voltage/low-power operation. For the cell structure of a ferroelectric memory, a 1-transistor/1-capacitor memory cell like a DRAM cell has been widely developed.
A ferroelectric memory cell stores the “1” or “0” state depending on whether the polarization is directed upward or downward, as shown in FIG.
27
. As shown in
FIG. 27
, a cell transistor
100
, which has a gate connected to a word line WL and a source connected to a bit line BL, is connected to a node C, i.e., an electrode of a capacitor
101
with other electrode connected to a plate line PL. The polarization amount of the ferroelectric capacitor depends on the time of voltage application to the ferroelectric capacitor. When the time is prolonged, the polarization amount becomes close to the saturated polarization amount. For this reason, even in a device, when the write time is prolonged, a sufficient polarization amount can be obtained, and the data holding characteristic improves.
In a conventional general
1
-transistor/
1
-capacitor memory cell, to increase the reliability of cell data holding, the voltage across the ferroelectric capacitor is held after the data write to obtain sufficient polarization. That is, after the active state is ended, the word line is set in the unselected state to confine the bit line potential in the node C shown in FIG.
27
. In this state, a write potential is applied to the ferroelectric capacitor by the potential difference between the node C and the plate line PL, thereby sufficiently writing the data.
A ferroelectric memory (to be referred to as a TC parallel unit series connection type ferroelectric memory hereinafter) has received a great deal of attention because of its high operation speed and high degree of integration, in which a unit cell is formed by connecting the two terminals of a capacitor (C) between the source and the drain of a cell transistor (T) and connecting a plurality of unit cells in series. This ferroelectric memory is described in “A Sub-40 ns Random-Access Chain FRAM Architecture with a 7 ns Cell-Plate-Line Drive,”, ISSCC Tech. Dig. Papers, pp. 102-103, Feb. 1999.
In this structure, a cell transistor
102
formed from an n-channel transistor and a capacitor
103
are connected in parallel to form one memory cell
104
, as shown in
FIG. 28. A
plurality of memory cells
104
are connected in series to form a memory cell block
105
. Pairs of memory cell blocks
105
are laid out in multiple stages (one stage in FIG.
28
), and each of the paired memory cell blocks
105
is arranged between a corresponding one of bit lines BL and BLB and a corresponding one of plate lines PL
1
and PL
2
. Block selection transistors
106
with gates connected to block selection lines BS
0
and BS
1
are connected between the bit lines BL and BLB and the memory cells
104
in the respective memory cell blocks
105
.
In the standby mode, all the word lines WL are set at “H” level, and the two electrodes of each capacitor are short-circuited. In the active mode, a selected word line WL changes from “H” level to “L” level, and the block selection line BS changes from “L” level to “H” level. After that, the plate line PL changes to Vdd level to apply a Vdd potential to a selected capacitor. Data is read from the memory cell to the bit line BL. An unselected capacitor is held in the short-circuit state. In this way, a random access is done.
FIG. 29
is a view showing the arrangement of a control circuit for controlling a read/write from/to a memory cell. This control circuit has multiple stages of first to third and fifth to ninth delay circuits
107
to
114
connected in series, NAND circuit
115
, inverter circuit
116
, and NOR circuit
117
. The control circuit receives a chip enable signal CE
1
and generates and outputs two chip enable delay signals CED
1
and CED
2
, address pass signal BADPAS, row address latch signal BRAT, row address enable signal RAE, block selection enable signal BSEBL, sense amplifier enable signal SAEBL, and plate line enable signal PLEBL.
The first chip enable delay signal CED
1
controls signals for driving a block selection line drive circuit (not shown), plate line PL, and sense amplifier (not shown) which control the memory cell array. The second chip enable delay signal CED
2
controls an address buffer (not shown) to control the timing of the word line WL and also controls the row address latch signal BRAT and row address enable signal RAE for driving the address buffer. The address pass signal BADPAS controls the timing to send an external address signal to the address buffer. The block selection enable signal BSEBL controls the block selection line drive circuit. The sense amplifier enable signal SAEBL controls the sense amplifier. The plate line enable signal PLEBL controls the plate line PL.
The chip enable signal CE
1
is the output signal from an input buffer (not shown) for receiving an external signal CEB, and is set at “H” level in the active mode and at “L” level at the standby mode.
FIG. 30
is a timing chart showing input and output signals and signals at the respective nodes in the circuits, shown in
FIGS. 28 and 29
, of the conventional TC parallel unit series connection type ferroelectric memory in the read mode. Referring to
FIG. 30
, the signals are synchronized at timings indicated by dotted lines.
The external chip enable signal CEB changes from “H” level to “L” level only during a predetermined period.
When the external chip enable signal CEB has changed from “H” level to “L” level, the chip enable signal CE
1
output from a chip enable buffer changes from “L” level to “H” level. When the external chip enable signal CEB has changed from “L” level to “H” level, the chip enable signal CE
1
changes from “H” level to “L” level.
After the elapse of time (
1
)+time (
2
) from the timing when the chip enable signal CE
1
changes from “L” level to “H” level, the first chip enable delay signal CED
1
changes from “L” level to “H” level. After the elapse of times (
1
) and (
2
)+time (
3
) from the timing when the chip enable signal CE
1
changes from “H” level to “L” level, the first chip enable delay signal CED
1
changes from “H” level to “L” level. The total time (
1
)+(
2
)+(
3
) is about 20 nsec.
After the elapse of time (
1
) from the timing when the chip enable signal CE
1
changes from “L” level to “H” level, the second chip enable delay signal CED
2
changes from “L” level to “H” level. When the first chip enable delay signal CED
1
has changed to “L” level, the second chip enable delay signal CED
2
changes from “H” level to “L” level.
When the chip enable signal CE
1
changes from “L” level to “H” level, the address pass signal BADPAS simultaneously changes from “H” level to “L” level.
After the elapse of time (
5
) from the change to “L” level, the address pass signal BADPAS changes from “” level to “H” level again.
When the second chip enable delay signal CED
2
has changed from “L” level to “H” level, the row address latch signal BRAT changes from “H” level to “L” level. After the elapse of time (
6
) from the timing when the change of second chip enable delay signal CED
2
has changed from “H” level to “L” level, the row address latch signal BRAT changes from “L” level to “H” level.
After the elapse of time (
7
) from the timing when the second chip enable delay signal CED
2
has changed from “L” level to “H” level, the row

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