Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-11-20

2003-11-25

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S207000, C365S189011, C365S189110, C365S189050, C365S230060, C365S230080

Reexamination Certificate

active

06654298

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a shift redundancy function.
(2) Description of the Related Art
If there is a defective line in a semiconductor memory device manufactured, it can be returned to normal by substituting other lines including a redundant line for the defective line by the use of a technique called shift redundancy.
FIG. 9
is a view for giving an overview of shift redundancy. In
FIG. 9
, a memory array
2
includes an ordinary line
2
a
and redundant line
2
b
. How to connect them is managed by a decoder
1
.
As shown in
FIG. 10
, it is assumed that a defective line is detected in the middle area of this semiconductor memory device. Then the decoder
1
can substitute other lines including the redundant line for the defective line by shifting all of the lines being on the right-hand side of the defective line to the right.
FIG. 11
is a circuit diagram for realizing this shift redundancy. In
FIG. 11
, an address latch circuit
20
latches an address signal input from the outside and provides it to a decoding circuit
21
.
The decoding circuit
21
decodes an address signal latched by the address latch circuit
20
, generates a selection signal for selecting a predetermined line in a memory array, and provides it to a word driver circuit
22
.
The word driver circuit
22
drives the memory array in compliance with a selection signal supplied from the decoding circuit
21
.
A fuse circuit
23
includes fuses the number of which corresponds to that of word lines in the memory array. If tests run after manufacture show that a predetermined word line in the memory array is defective, information showing the defective line will be stored by blowing fuses corresponding to the position (address) of the defective line by the use of an external unit.
A decoding circuit
24
decodes information showing a defective line held in the fuse circuit
23
, generates an indicating signal that indicates the defective line from among word lines, and provides it to a redundant circuit
25
.
The redundant circuit
25
controls the word driver circuit
22
in compliance with an indicating signal and substitutes other lines including a redundant line for a defective line.
Operation in the above conventional semiconductor memory device will now be described.
If tests run after manufacture show that a predetermined word line in the memory array is defective, a fuse in the fuse circuit
23
corresponding to the defective line will be blown.
It is assumed that a semiconductor memory device in which fuses corresponding to a defective line have been blown in this way is mounted in a predetermined circuit and that power is applied to it. First, the fuse circuit
23
generates a signal corresponding to how fuses are blown (address signal showing the defective line) and provides it to the decoding circuit
24
.
The decoding circuit
24
decodes the signal supplied from the fuse circuit
23
, generates an indicating signal, and provides it to the redundant circuit
25
.
The redundant circuit
25
refers to the indicating signal supplied from the decoding circuit
24
, shifts word lines by controlling the word driver circuit
22
, and substitutes other lines including a redundant line for the defective line (see FIG.
10
).
When the shift redundancy is completed, the semiconductor memory device begins to accept an address signal and the address latch circuit
20
latches an address signal input.
The decoding circuit
21
decodes the address signal latched by the address latch circuit
20
, generates a selection signal, and provides it to the word driver circuit
22
.
The word driver circuit
22
has performed shift redundancy on the basis of instructions from the redundant circuit
25
, so the word driver circuit
22
properly shifts the selection signal supplied from the decoding circuit
21
and provides it to the memory array. This can exclude the defective line from lines to be accessed and substitute the redundant line for the defective line.
FIG. 12
is a view for giving an overview of a circuit pattern formed in the case of the circuit shown in
FIG. 11
being mounted on a semiconductor substrate. In this example, the decoding circuit and fuse circuit are located along a side of the memory array. Hatched areas in the decoding circuit are the redundant circuits. Each of the right and left halves of the memory array is a redundancy unit. If a defective line exists in each unit, the operation in each unit of substituting a redundant line for a defective line will be performed independently.
As stated above, if there is a one-to-one relationship between a memory array on which shift redundancy is performed and a fuse circuit, the only thing to do is to newly add a block corresponding to a redundant line. Shift redundancy therefore can be realized easily.
As shown in
FIG. 11
, to realize shift redundancy, selection wirings for shift redundancy must be formed separately from ordinary selection wirings. There are many wirings especially after the decoding circuit
21
and redundant circuit
25
, so the penalties of wirings can arise, depending on a circuit layout.
Furthermore, as shown in
FIG. 13
, with a semiconductor memory device, such as a fast cycle random access memory (FCRAM), consisting of a plurality of subblocks, there is a technique in which the plurality of subblocks share a fuse. In this case, “subblock” is a memory array unit including one redundant line. In this example, hatched areas are redundant circuits, so there are two subblocks in the horizontal and vertical directions respectively. That is to say, this semiconductor memory device consists of a total of 4 (=2×2) subblocks.
In this example, two subblocks located in the vertical direction share one fuse circuit. Therefore, as shown in
FIG. 14
, if there is a defective line in one of the two subblocks located in the vertical direction, shift redundancy is performed on both of them. In this example, the fourth line from the left and the rightmost line are defective ones. The leftmost redundant lines in the left and right subblocks are substituted for these defective lines.
If a plurality of subblocks located in the vertical direction share the same fuse circuit in this way, a decoding circuit in each subblock and the fuse circuit must be connected with a wiring. Therefore, as shown in
FIGS. 13 and 14
, some of these wirings must pass over a subblock, resulting in a stronger probability of the penalties of wirings arising and difficulty in a decoder layout.
With a memory layout of a spread type, memory arrays located in the vertical direction can share a fuse circuit. In this case, there is no need to locate lines over a memory array. However, this technique is not applicable to cases where more than two memory arrays exist.
SUMMARY OF THE INVENTION
In order to address such problems, the present invention was made. An object of the present invention is to reduce the probability of the penalties of wirings arising and to make the arrangement of recorders easy, especially in a semiconductor memory device having a plurality of subblocks.
In order to achieve the above object, a semiconductor memory device having a shift redundancy function is provided. This semiconductor memory device comprises an address input circuit for receiving an address signal input, a drive circuit for driving a memory array in compliance with the address signal, a signal line for connecting the address input circuit and the drive circuit, a redundant circuit located near the drive circuit for substituting other lines including a redundant line for a defective line in the memory array, a defective line information store circuit for storing information showing the defective line, and a supply circuit for supplying information stored in the defective line information store circuit to the redundant circuit via the signal line.
The above and other objects, features and advantages of the present inventio

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