Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-06-20

2003-11-11

Ellis, Kevin L. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S105000

Reexamination Certificate

active

06647478

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which dynamic RAMs (DRAM cells) are accumulated, and particularly to a DRAM which can improve the data transfer efficiency in a read/write mixed cycle in a high-speed random access cycle.
Of the MOS type semiconductor memory devices, the DRAM is most highly integrated, since the memory cells constituting the device are comparatively simple in structure. Hence, at present, the DRAM is used as a main memory of any type of computer equipment. Recently, as the performance of the microprocessor (MPU) has been rapidly improved, various DRAMs having high-speed data cycle functions to increase the capacity of memories have been proposed or mass production thereof has begun. Typical examples of these DRAMs are a synchronous DRAM (hereinafter referred to as a SDRAM) and a double data rate SDRAM (hereinafter referred to as a DDR-SDRAM). The SDRAM receives and transmits any input and output information in synchronism with a system clock. The DDR-SDRAM performs a similar operation and is accessible at both up and down edges of a clock as triggers.
Further, a rambus DRAM (hereinafter referred to as an RDRAM) and the like have been developed, which can transfer data at higher speed by a protocol-based command. Therefore, the conventional asynchronous DRAMs will inevitably be replaced by synchronous DRAMs in the future.
The synchronous DRAMs are characterized in that the maximum bandwidth (data transfer rate) is very high. For example, the latest SDRAM achieves 100 Mbps in the maximum bandwidth.
Further, it is expected that the maximum bandwidth in the future is 200 Mbps in a DDR-SDRAM and 800 Mbps in an RDRAM.
However, such a high bandwidth is limited to a burst access only in a specific row direction in a memory space.
In other words, in random access wherein the row address is changed, the access speed is as low as that in the conventional asynchronous DRAM. To increase the access speed, the computer system including a DRAM as a main memory generally employs a hierarchical memory structure.
More specifically, a cache memory comprising a SRAM, which is accessible at a higher speed as compared to a DRAM, is interposed between the MPU and the DRAM, and part of the information stored in the DRAM is cached in the SRAM. In this structure, the MPU generally accesses the cache memory accessible at a higher speed. It accesses the DRAM only when it receives an access command for an address space which is not cached by the cache memory. By means of this structure, even if there is a difference in speed performance between the MPU and the DRAM, the performance of the computer system can be considerably improved.
However, in case of a cache miss, it is necessary to read information from the DRAM. In particular, when another address in the same block of the DRAM memory space is accessed, the waiting time of the MPU becomes the longest. The problem of the waiting time in, for example, an SDRAM, will be described below with reference to FIG.
1
.
FIG. 1
shows an example of the timing chart of a read operation of an SDRAM. In the aforementioned computer system using the hierarchical memory structure, if a cache miss occurs and the SDRAM as the main memory must be accessed, a precharge command (PRECHARGE) is issued from the system at a time t
1
to precharge a currently active address of the memory. After a predetermined time elapses, an activate command (ACTIVE) is issued from the MPU, so that the bank corresponding to a required memory space is activated. Further, after the elapse of a predetermined time, a read command (READ) is issued. After a time t
2
after a predetermined time has elapsed since the read command, data of a predetermined burst length is read from the SDRAM in synchronism with a clock.
As shown in
FIG. 1
, the maximum bandwidth is very high when data is read successively in synchronism with clocks. However, in case of a cache miss, the practical bandwidth with respect to random access is considerably low. In other words, in a period between the times t
1
and t
2
, the time when data is not read out, namely, the waiting time of the MPU, is long.
In the case of the SDRAM of the specification as shown in
FIG. 1
, the maximum bandwidth in the random access time is only 36% of that of the burst access time. It is highly possible that the slow access will be a bottleneck for further improvement of the performance of the computer system.
In consideration of the above situations, there has been an increased demand for a high-performance DRAM which realizes a higher access and a shorter cycle time. Particularly, in a multi MPU system such as a current high-performance server machine, not only high-speed burst transference but also high-speed random access is regarded as very important. Further, in a household multimedia system mainly for the purpose of real-time reproduction of an animation image in the future, there will be a demand for a similar DRAM that allows high-speed random access.
The DRAMs, which will meet such a demand, are an enhanced SDRAM (hereinafter referred to as an ESDRAM) as shown in
FIG. 2
published by Enhanced Memory Systems Inc. and a virtual channel memory (hereinafter referred to as VCM) as shown in
FIG. 3
published by NEC Corporation.
In the ESDRAM, however, each bank incorporates a SRAM cache
101
, as shown in FIG.
2
. In the VCM, 161K-caches
102
comprising register circuits are mounted. Thus, the DRAM of this kind has a great number of cache memories in addition to the conventional DRAM memory cell array. Since high-speed access and a short cycle are realized by many cache memories, overheads are high relative to the chip size. Therefore, it is difficult to lower the cost.
Both high-speed random access and low cost can be achieved by a method in which, the idea of “the page cycle” function, an operation mode of the conventional DRAM, is not used. According to this method, when a very little amount of cell data has been detected and amplified in the DRAM operation, a precharge operation is automatically stated immediately.
More specifically, as shown in
FIG. 4
, when a read command (RCMD#
1
) is issued at a time t
1
, activation of a word line (WL) is started and cell data is read out to a group of bit lines (bBL/BL). Thereafter, a sense amplifier is activated at a time t
2
. When cell data is detected by the sense amplifier, a column selection line (CSL) is activated at a time t
3
, and bit line data is transferred to a data line (not shown) in the chip and output through the data line to the outside of the chip. The sense amplifier amplifies the cell data to a desired voltage in a period of time in which data is transferred through the line between the data line and the read out section in the chip. When the amplification is completed at a time t
4
, a series of precharge operations, e.g., inactivation of the word line (WL) and precharge of the bit line, are automatically started. Thus, although the DRAM does not have a page access function, a series of access sequences can be completed in the minimum time, resulting in high-speed random access in a short cycle.
Further, an improved synchronous memory for improving the data transfer performance to the maximum has been devised. In the devised memory, a so-called read latency (R.L.), i.e., a time between setting of a read command and establishment of read data, is set to the same clock cycle value as that of a so-called write latency (W.L.), i.e., a time between setting of a write command and preparation of effective write data. A no bus latency SRAM (NoBL SRAM) proposed by Cypress Semiconductor Corporation is an example of such a memory.
The conventional pipeline SRAM requires a period of four clocks to realize a read/write mixed cycle, as shown in FIG.
5
. On the other hand, as shown in
FIG. 6
, the NoBL SRAM requires two clocks, i.e., half the clocks required by the conventional art.
As described above, R.L. and W.L. are set to the same clock cycle value (two clock cycles in
FIG. 6
) in the NoBL SRAM. As a resu

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