Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-11-13

2003-05-27

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230030, C365S233100

Reexamination Certificate

active

06570802

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for refreshing a semiconductor memory device, in particular, a DRAM (Dynamic Random Access Memory).
BACKGROUND OF THE INVENTION
In recent years, as miniaturization and lower power consumption of a system have been developed, a lower power consumption of semiconductor device has been demanded strongly. In a semiconductor memory device such as a DRAM that requires refresh, not only low power consumption during the operation but also the reduction of refresh current during standby (in the sleep mode, etc.) has been demanded.
A conventional refreshing function will be explained in the following. In a DRAM in which a memory cell is formed of a capacitor, with the passage of a predetermined time, data stored as an electric charge in the memory cell are lost by a leak current. Therefore, in order to rewrite and maintain data stored in the memory cell, a refresh operation is required. In the memory matrix composed of a plurality of rows and columns of the memory cell, the refresh operation in a DRAM is carried out as follows. One line of rows (a word line) is selected, and data with respect to all the memory cells on the word line are read out, amplified and rewritten. These operations are carried out repeatedly with respect to all word lines.
The DRAM refresh operation includes the refresh operation carried out by interrupting the random access operation accompanying the reading out/writing of data with respect to the memory cell, and the refresh operation carried out during the data retaining mode, for example, during a battery back-up period.
The former refresh operation carried out during the random access operation is classified into two types: one is a row address strobe signal
6
(hereinafter referred to as RAS) only refresh method in which a row address for refresh is provided from the outside and the refresh is carried out during a period from a rise of a row address strobe signal RAS and a fall thereof, and another is an auto-refresh method in which a refresh request signal is provided from the outside to carry out refresh by switching the row address from the outside address to the address supplied by the refresh address counter contained in the DRAM.
The latter refresh operation, that is, the refresh operation in the data retaining mode, includes a self-refresh method. In the self-refresh method, in accordance with the refresh request signal automatically generated by an inner timer, the refresh is carried out by using an output from the built-in refresh address counter as a row address, thereby refreshing at the constant period without providing a control signal from the outside.
These conventional DRAM refresh methods will be explained with reference to the drawings.
FIG. 14
shows an example of a configuration of a circuit for carrying out a conventional refresh method. In
FIG. 14
, reference numeral
1
denotes a memory cell array;
2
denotes a row decode circuit for selecting a row line (hereinafter, referred to as a word line) according to a given row address;
3
denotes a column decode circuit for selecting a bit line according to the given column address;
4
denotes a sense amplifier and I/O bus column for carrying out the operation to read out and write data with respect to the memory cell that is present at an intersection between a word line selected by the row decode circuit
2
and a bit line selected by the column decode circuit
3
.
Reference numeral
5
denotes a timing generation circuit for generating a timing signal to read out and write data with respect to the memory cell in the memory cell array
1
. This timing generation circuit
5
generates a necessary timing signal
12
using an OR signal
10
output from an OR circuit
15
and a column address strobe signal
11
(hereinafter, referred to as CAS). Into the OR circuit
15
, a RAS
6
, an auto-refresh signal
7
(hereinafter, referred to as AUT) used for the row address strobe signal at the time of the auto-refresh time and an address strobe signal for self-refresh
9
(an output signal from the timer generation circuit A
8
) are input.
The timer circuit A
8
receives a self-refresh mode control signal (hereinafter, referred to as SLF)
13
and outputs “L” when SLF=“L” is satisfied, and outputs an address strobe signal for refresh when SLF=“H” is satisfied. An example of the circuit and the operation of the timer circuit A
8
will be explained hereinafter.
The address generation circuit A
14
is composed of a refresh address counter generating an entire row address. As a clock input for count-up of the refresh address counter, the OR signal
10
output from the OR circuit
15
is used. With this configuration, which is similar in the general operation, in accordance with the rise of a row address strobe signal for auto-refresh and self-refresh, addresses are counted up and the entire memory regions are refreshed.
Furthermore, during the general operation, for selecting the address from the outside, an output of an address generation circuit A
14
and an outside row address
16
are switched by the selector
17
by using an OR signal
18
, which is output from the OR circuit
15
a
using the row address strobe signal for self-refresh
9
(an output signal from the timer circuit A
8
) and the auto-refresh control signal
7
.
Next, an example of the timer circuit A
8
and the address generation circuit A
14
will be explained.
First, the operation of the timer circuit A
8
will be explained with reference to the example of the circuit shown in FIG.
15
. As shown in
FIG. 15
, the timer circuit A
8
includes an oscillation circuit
20
, a frequency dividing circuit A
21
and a signal generation circuit
22
. When a RST (reset) signal
23
is “L”, “L” is output as an output signal
24
of the signal generation circuit
22
, and in the oscillation circuit
20
, the output is fixed to “H”. When the RST signal
23
becomes “H”, the oscillation circuit
20
operates, a periodic pulse generated from the oscillation circuit
20
is frequency-divided by the frequency dividing circuit A
21
, and a periodic signal is generated by the signal generation circuit
22
. The periodic signal has “H” period corresponding to the delay amount by a delay circuit
25
and toggles at the period of the pulse frequency-divided by the frequency dividing circuit A
21
. The delay circuit
25
is composed of plural stages of buffer circuits, etc.
FIG. 16
is an example of the frequency dividing circuit A
21
. The frequency dividing circuit A
21
is composed by using a counter circuit
26
with load. Using the load value of the counter circuit
26
, the frequency-dividing ratio is determined.
FIG. 16
shows an example of a quarter frequency circuit. By applying this quarter frequency circuit, the period of the pulse generated from the oscillation circuit
20
becomes 4 times. The counter circuit
26
with load may be composed of, for example, as shown in
FIG. 17
, a D-flip flop
27
, an adder
28
and an AND gate
29
.
Next, the address generation circuit A
14
will be explained with reference to an example of a circuit shown in FIG.
18
. As shown in
FIG. 18
, the address generation circuit A
14
includes a counter
19
. The number of the bits of the counter
19
is the same as the number of the bits of the row address.
FIG. 18
shows a configuration of the circuit for an 8-bit row address. As the counter
19
, for example, an embodiment of a circuit shown in
FIG. 3
is used. The counter shown in
FIG. 3
includes a D-flip flop
30
, an adder
31
and an AND gate
32
.
FIG. 3
shows an example of a 4-bit counter. However, by using a circuit unit
33
for the higher bits repeatedly, it is possible to increase the number of bits of the counter.
As is apparent from the above explanation, in the conventional circuit, in both the auto-refresh time and self-refresh time, all data in the memory cell array are refreshed. However, when all data in the memory cell array
1
are refreshed, the electric power consumption during the syst

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