Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-03-22

2003-05-20

Phan, Trong (Department: 2812)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S203000, C365S207000

Reexamination Certificate

active

06567330

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device with a current-read-type memory cell, in which data is judged on the basis of the presence or absence of a cell current or the amount of the cell current. More specifically, the present invention relates to a data sense circuit for the semiconductor memory device.
2. Related Background Art
In a related DRAM, a memory cell is composed of an MOS transistor and a capacitor. The scale-down of the DRAM has been remarkably advanced by the adoption of a trench capacitor structure and a stacked capacitor structure. At present, the cell size of a unit memory cell is scaled down to an area of 2 F×4 F=8 F
2
, where F is a minimum feature size. However, it becomes difficult to secure the same downsizing trend of cell size as before. Because, there are a technical difficulty that the transistor has to be a vertical type, a problem that electric interference between adjacent memory cells increases, and in addition difficulties in terms of manufacturing technology including fabrication, film formation, and the like.
On the other hand, some proposals for a DRAM in which a memory cell is composed of one transistor without using a capacitor are made as mentioned below.
(1) JOHN E. LEISS et al, “dRAM Design Using the Taper-Isolated Dynamic Cell” (IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.SC-17, NO.2, APRIL 1982, pp337-344)
(2) Japanese Patent Laid-open Publication No. H3-171768
(3) Marnix R. Tack et al, “The Multistable Charge-Controlled Memory Effect in SOI MOS Transistors at Low Temperatures” (IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL, 37, MAY, 1990, pp1373-1382)
(4) Hsing-jen Wann et al, “A Capacitorless DRAM Cell on SOI Substrate” (IEDM93, pp635-638)
A memory cell in the document (1) is composed of MOS transistors, each of which has a buried channel structure. Charge and discharge to/from a surface inversion layer is performed using a parasitic transistor formed at a taper portion of an element isolation insulating film to perform binary storage.
A memory cell in the document (2) uses MOS transistors which are well-isolated from each other and uses a threshold voltage of the MOS transistor fixed by a well potential as binary data.
A memory cell in the document (3) is composed of MOS transistors on an SOI substrate. A large negative voltage is applied from the SOI substrate side, and by utilizing accumulation of holes in an oxide film of a silicon layer and an interface, binary storage is performed by emitting and injecting these holes.
A memory cell in the document (4) is composed of MOS transistors on an SOI substrate. The MOS transistor is one in terms of structure, but here a structure, in which a reverse conduction-type layer is formed on top of the surface of a drain diffusion region, whereby a P-MOS transistor for write and an N-MOS transistor for read are substantially combined integrally, is adopted. With a substrate region of the N-MOS transistor as a floating node, binary data are stored by its potential.
However, in the document (1), the structure is complicated and the parasitic transistor is used, whereby there is a disadvantage in the controllability of its characteristic. In the document (2), the structure is simple, but it is necessary to control potential by connecting both a drain and a source of the transistor to a signal line. Moreover, the cell size is large and rewrite bit by bit is impossible because of the well isolation. In the document (3), a potential control from the SOI substrate side is needed, and hence the rewrite bit by bit is impossible, whereby there is a difficulty in controllability. In the document (4), a special transistor structure is needed, and the memory cell requires a word line, a write bit line, a read bit line, and a purge line, whereby the number of signal lines increases.
The memory cell composed of one transistor in the related art stores data on the basis of a gate threshold voltage difference cased by a potential difference of a channel body. This is basically different from the data storage system using accumulation of electrical charge in a capacitor. Therefore, in the memory cell composed of one transistor, the presence or absence of a cell current passed through the memory cell is detected, or whether the cell current is large or small is detected, in order to judge the data stored in the memory cell. That is, the memory cell composed of one transistor is a current-read-type memory cell.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a semiconductor memory device comprising:
a memory cell array which includes memory cells for holding data;
a reference current generating circuit which generates a reference current;
a reference voltage generating circuit which generates a reference voltage in a reference node on the basis of the reference current generated by the reference current generating circuit;
a first sense circuit which generates an output current on the basis of a cell current of the selected memory cell and which generates a data voltage in a sense node on the basis of the output current and the reference current; and
a second sense circuit which detects the data held in the selected memory cell by comparing the data potential in the sense node with the reference voltage in the reference node.


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Leiss, et al., “dRAM Design Using the Taper-Isolated Dynamic RAM Cell”, IEEE Journal of Solid-State Circuits, vol. SC-17, No. 2, Apr. 1982, pp. 337-344.
Tack, et al., “The Multistabel Charge-Controlled Memory Effect in SOI MOS Transistors at Low Temperatures”, IEEE Transactions on Electron Devices, vol. 37, No. 5, May 1990, pp. 1373-1382.
Wann, et al., “A Capacitorless DRAM Cell on SOI Substrate”, IEDM 1993, pp. 635-638.

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