Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2002-05-14
2003-09-09
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S201000, C365S189090
Reexamination Certificate
active
06618298
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technique effective specially for controlling switching of a voltage at the time of a test performed for a semiconductor memory in/from which information can be written/erased electrically. More particularly, the present invention relates to a technique to be employed effectively for flash memories.
A flash memory employs non-volatile elements as its memory cells, each of which is comprised of a MOSFET with a double gate structure having a control gate and a floating gate. The flash memory stores information by changing the amount of the charge accumulated in the floating gate of the MOSFET, thereby switching the threshold voltage in the MOSFET between high and low states.
In a flash memory, the threshold voltages in the memory cells are distributed within a certain range after data is written or erased in/from them, since the threshold voltage is varied not only among memory cells, but also in a single memory cell after such the writing/erasing. Generally, a flash memory is provided with a power supply circuit that includes a step-up circuit and configured so as to generate a high voltage required for writing and erasing. This is why the writing voltage and the erasing voltage generated by the power supply circuit come to be varied among chips and this voltage variation causes the threshold voltage to be varied among memory cells in each chip.
In order to avoid such the problem, each chip is checked for defect/reliable, as well as for the performance by checking how the threshold voltages in memory cells are changed, that is, how they are distributed in a test mode after data is written/erased in/from those memory cells. To make it possible to perform such a test (hereinafter, to be referred to as a threshold voltage distribution test), each chip is usually configured so as to enable data to be read from a word line after a desired voltage is applied to the word line from an external tester.
SUMMARY OF THE INVENTION
In such a threshold voltage distribution test, a selected word line must be changed to another to detect the threshold voltage in every memory cell in the object memory array. In addition, a decoder circuit must be driven to apply a voltage to a desired word line from the tester. In the case where the decoder circuit is driven while a high voltage is applied to a word line from the tester at this time, the MOSFETs, which compose the driver circuit and the power supply circuit of the word line, are switched over while a high voltage is applied to them, thereby a drain current flows in them. Consequently, a problem such as element degradation might arise. To avoid such the problem, therefore, in a threshold voltage distribution test for a conventional flash memory, the conventional tester has been configured so as to lower the voltage supply at the tester side to the Vcc once when a word line is changed to another (hereinafter, this operation is referred to as a voltage reset operation).
As a result, the word line change takes much time, causing the test time to be extended. In addition, the tester is required to reset the voltage at each word line change, thereby the tester load has increased. This has also been a problem.
Under such circumstances, it is an object of the present invention to shorten the test time and reduce the load of the tester without changing the voltage supplied from the tester during a test performance for respective semiconductor memory devices provided with a switch enabled to turn on/off the voltage supplied to an external terminal and transmitted to the memory array at the time of a test and enabled to use a voltage supplied from an external device for the test.
It is another object of the present invention to omit changes of a voltage supplied from the tester at each word line change in a threshold voltage distribution test performance for respective semiconductor memory devices provided with memory cells, each being enabled to store information therein according to the high/low state of the threshold voltage, thereby the test time is shortened and the load of the tester is reduced.
The above and further objects, as well as novel features of the present invention will be apparent from the description and the accompanying drawings in this specification.
Hereinafter, the typical one of the present invention objects disclosed in this specification will be briefly described.
In such a semiconductor memory device as a flash memory, a switching element comprised of a single channel MOS transistor is provided at a halfway of a path that transmits a voltage supplied from an external terminal to a memory array at the time of a test performance.
Concretely, in a semiconductor memory device provided with a memory array consisting of a plurality of memory cells, a plurality of selection lines connected to selection terminals of a plurality of memory cells disposed in a first direction, and a plurality of signal lines connected to data input/output terminals of a plurality of memory cells disposed in a second direction and formed as a semiconductor integrated circuit on a semiconductor chip, the semiconductor chip is provided with an external terminal enabled to supply a first voltage to the memory array at the time of a test performance in addition to a power supply terminal to which a supply voltage required for driving all the circuits formed on the chip is supplied, the first voltage being different from the supply voltage. A first switching element comprised of an N-channel or P-channel MOS transistor is provided at a halfway of a path that transmits the first voltage from the external terminal to the memory array.
According to the above described means, the switching element is turned off to shut off the voltage to be supplied to the memory array, thereby there is no need to change the voltage at each test performance. Consequently, the test time is shortened and the load of the tester is reduced.
At this time, the first voltage supplied to the memory array from outside the semiconductor chip at the time of a test performance may be supplied to any of the selection lines and the signal lines.
Each of the above described memory cells is comprised of a non-volatile memory element enabled to store information according to the high/low state of its threshold voltage. In a semiconductor memory device comprised of such non-volatile memory elements, a test performance is required to detect the distribution of the threshold voltages in the memory elements by varying the voltage applied to a word line to read data from each memory cell connected to the word line. And, the present invention has successfully eliminated such the resetting of the voltage that has been required conventionally at each word line change for this test performance. This is why the test time is shortened and the load of the tester is reduced.
Furthermore, the above described memory cells are all enabled to be written information electrically and the above described semiconductor chip is provided with a voltage generator that generates a second voltage, which is different from the supply voltage. The second voltage generated by the voltage generator is transmitted to the memory array when information is written therein. And, a second switching element is provided at a halfway of a path that transmits the second voltage to the memory array. Consequently, when the semiconductor chip is configured so that both of the first and second voltages are supplied to the memory array through a common path, it is possible to avoid transmission of the first voltage to the voltage generator while the first switching element is turned on. The first voltage supplied to the external terminal is thus supplied to the memory array.
The semiconductor chip is also provided with a third switching element enabled to supply the supply voltage to the memory array instead of the first voltage when the first switching element is turned off and the second switching element is turned on. Consequently, the supply voltage can be supplied to the memory
Honma Kazuki
Kuwahara Shuichi
Wada Masashi
Lam David
Miles & Stockbridge P.C.
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