Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1996-04-18

1997-04-22

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Data refresh

365149, 36518901, 3652335, G11C 700

Patent

active

056234511

ABSTRACT:
A DRAM includes an address registration circuit for registering an address of a row including a memory cell having poor data retention characteristic, and an entire refresh period setting circuit for setting a multiple value m of a refreshing period. The row of the registered address is refreshed in the refresh period, and other rows are refreshed in a period m times the refreshing period. Therefore, as compared with the prior art in which all the rows are refreshed in the refresh period set for the rows including the memory cell having poor data retention characteristic, power consumption can be reduced. Further, as compared with another prior art in which the refresh period setting circuit is provided for each row, the number of circuits can be reduced.

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