Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-11-29

2003-03-04

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Fet configuration adapted for use as static memory cell

C257S391000, C257S392000, C257S204000

Reexamination Certificate

active

06528897

ABSTRACT:

Applicant hereby incorporates by reference Japanese Application No. 2000-363207, filed Nov. 29, 2000, in its entirety.
TECHNICAL FIELD
The present invention relates to semiconductor memory devices, including an SRAM (static random access memory) with an improved &bgr; ratio.
RELATED ART
A conventional SRAM often uses a CMOS cell that uses six transistors, as it has a large operation margin and a small data retaining current.
In order to stabilize the operation of the SRAM, the &bgr; ratio between the drive MOS transistor and the transfer MOS transistor needs to be made large. For this purpose, these transistors are conventionally made in different sizes on their designs to secure a sufficient &bgr; ratio. For example, as a measure to increase the &bgr; ratio, sizes (gate width/gate length) of transfer MOS transistor and drive MOS transistor are changed. More specifically, when gate width/gate length of a transfer MOS transistor are respectively 0.18/0.18, gate width/gate length of a drive MOS transistor are respectively 0.22/0.12, to thereby increase the &bgr; ratio.
It is noted that the aforementioned &bgr; is a parameter that is defined by &bgr;=&mgr; CoxWeff/Leff, where &mgr; is carrier mobility, Cox is a capacitance of gate oxide film, Weff is an effective channel width, and Leff is an effective channel length. The &bgr; ratio is defined by (the capability of a drive MOS transistor)/(the capability of a transfer MOS transistor).
SUMMARY
Embodiments relate to a semiconductor memory device including a pair of transfer MOS transistors controlled by a word line and a pair of data retaining flip-flop circuits formed from serially connected load elements and drive MOS transistors, wherein the transfer MOS transistors each has a threshold voltage greater than a threshold voltage of each of the drive MOS transistors.
Embodiments also relate to a semiconductor memory device including a pair of transfer MOS transistors controlled by a word line and a pair of data retaining flip-flop circuits formed from serially connected load elements and drive MOS transistors, wherein a gate electrode of each of the transfer MOS transistors has an impurity concentration lower than an impurity concentration of a gate electrode of each of the drive MOS transistors.
Embodiments also relate to a semiconductor device including an SRAM. The device includes a first transistor including a gate electrode connected to a word line, the first transistor also including a first end connected to a first bit line. The device also includes a second transistor including a gate electrode connected to the word line, the second transistor also including a first end connected to a second bit line. The device also includes a third transistor including a gate electrode, the third transistor including a first end connected to a ground potential and a second end connected to a second end of the first transistor. The device also includes a fourth transistor including a gate electrode, the fourth transistor including a first end connected to the ground potential and a second end connected to a second end of the second transistor. The device also includes a fifth transistor including a gate electrode, the fifth transistor including a first end connected to a power supply and a second end connected to the second end of the first transistor. The device also includes a sixth transistor including a gate electrode, the sixth transistor including a first end connected to the power supply and a second end connected to the second end of the second transistor. The gate electrode of the third transistor and the gate electrode of the fifth transistor are each connected to the second end of the second transistor. The gate electrode of the fourth transistor and the gate electrode of the sixth transistor are each connected to the second end of the first transistor. In addition, the first and second transistors have a threshold voltage that is greater than a threshold voltage of the third and fourth transistors.
Embodiments also relate to a method for forming a semiconductor device including forming a pair of transfer MOS transistors controlled by a word line, and forming a pair of data retaining flip-flop circuits from serially connected load elements and drive MOS transistors. The method includes forming the transfer MOS transistors to have a threshold voltage greater than that of the drive MOS transistors.
Embodiments also relate to a method for forming a semiconductor device including forming a pair of transfer MOS transistors controlled by a word line, and forming a pair of data retaining flip-flop circuits from serially connected load elements and drive MOS transistors. The method includes forming a gate electrode of each of the transfer MOS transistors to have a lower impurity concentration than that of a gate electrode of each of the drive MOS transistors.


REFERENCES:
patent: 07-022521 (1995-01-01), None
patent: 08-148582 (1996-06-01), None
patent: 08-316338 (1996-11-01), None
patent: 09-017962 (1997-01-01), None
Pater Van Zant, Microchip Fabrication, 2000, Mc Graw-Hill Companies, Fourth Edition, p. 74.

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