Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
Reexamination Certificate
2001-06-08
2003-05-27
Nguyen, Cuong Quang (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Fet configuration adapted for use as static memory cell
C257S904000, C257S903000
Reexamination Certificate
active
06570264
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to semiconductor memory devices such as SRAMs (static random access memories).
2. Description of Related Art
SRAMs, one type of semiconductor memory devices, do not require a refreshing operation, and therefore have characteristics that can simplify a system in which they are incorporated and facilitate lower power consumption. For this reason, the SRAMs are prevailingly used as memories for hand-carry type equipment, such as cellular phones.
In manufacturing SRAMs, first, mask patterns are made based on patterns that are designed by the designers. Resists are exposed using the mask patterns to make resist patterns. Using the resist patterns, conduction layers and the like formed on a semiconductor substrate are selectively etched to form patterns for a memory circuit on the semiconductor substrate.
In the manufacturing of the SRAM described above, when a mask pattern is completely identical with a designed pattern, a resist pattern is not formed faithfully with respect to the designed pattern due to light proximity effect. In particular, narrow end sections of wirings have small focusing margins in the exposure and they cause rounded or receded end sections in the resist pattern. Also, when contact holes are located in end sections of wirings, problems occur. For example, an enclosure (an extra coverage for the wiring above or below the contact hole) of the contact deteriorates, which results in an increased resistance, opens the connection, and causes other problems. For this reason, mask patterns, with the light proximity effect being corrected with respect to the designed patterns, are used. However, patterns with finely corrected measurements are required to correct the light proximity effect, and therefore the cost for the masks increases. Also, steps for confirming the corrected patterns are required, which result in a longer period for developing SRAMs and an increase in development costs.
Also, hand-carry type equipment on which SRAMs are mounted need to be reduced in size, and therefore the memory size of the SRAMs must be reduced.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a highly reliable semiconductor memory device that enhances manufacturing and reproducibility of wiring patterns.
It is another object of the present invention to provide a semiconductor memory device that can alleviate the correction of the light proximity effect.
It is a further object of the present invention to provide a semiconductor memory device that can reduce the size of memory cells.
In accordance with the present invention, a semiconductor memory device has a memory cell that includes a first driver transistor, a second driver transistor, a first load transistor, a second load transistor, a first transfer transistor and a second transfer transistor. The semiconductor device includes a first drain—drain connection layer and a second drain—drain connection layer. The first drain—drain connection layer connects a drain region of the first driver transistor and a drain region of the first load transistor. The second drain—drain connection layer connects a drain region of the second driver transistor and a drain region of the second load transistor. Each of the first drain—drain connection layer and the second drain—drain connection layer includes a first contact end section, a second contact end section, a linear section and an extension section. The first contact end section of the first drain—drain connection layer is a portion that connects to the drain region of the first driver transistor. The second contact end section of the first drain—drain connection layer is a portion that connects to the drain region of the first load transistor. The linear section of the first drain—drain connection layer is a portion that linearly extends from the first contact end section of the first drain—drain connection layer and reaches the second contact end section of the first drain—drain connection layer. The extension section of the first drain—drain connection layer is a portion that extends from the second contact end section of the first drain—drain connection layer in a direction toward a location where the second drain—drain connection layer is located. The first contact end section of the second drain—drain connection layer is a portion that connects to the drain region of the second driver transistor. The second contact end section of the second drain—drain connection layer is a portion that connects to the drain region of the second load transistor. The linear section of the second drain—drain connection layer is a portion that linearly extends from the first contact end section of the second drain—drain connection layer and reaches the second contact end section of the second drain—drain connection layer. The extension section of the second drain—drain connection layer is a portion that extends from the second contact end section of the second drain—drain connection layer in a direction toward a location where the first drain—drain connection layer is located.
In accordance with the present invention, the extension section prevents the second contact end sections of the drain—drain connection layer from being rounded or receded. Therefore, the enclosure of a contact hole disposed at the second contact end section is prevented from deterioration. Accordingly, in accordance with the present invention, process margins for a semiconductor memory device and its reliability can be enhanced.
Also, in accordance with the present invention, the extension sections correct the light proximity effect. Therefore, devices, such as shelves or the like to correct the light proximity effect, do not need to be added to the second contact end section of the second drain—drain connection layer. Accordingly, the correction of the light proximity effect can be alleviated, and the cost for semiconductor memory devices can be accordingly reduced.
In accordance with the present invention, another conduction layer is not located between the extension section of the first drain—drain connection layer and the extension section of the second drain—drain connection layer. In accordance with the present invention, since other conduction layers are not located in the region described above, the extension section can be formed without enlarging the area of the memory cell.
In accordance with the present invention, a distance between the first contact end section of the first drain—drain connection layer and the first contact end section of the second drain—drain connection layer is longer than a distance between the extension section of the first drain—drain connection layer and the extension section of the second drain—drain connection layer. In accordance with the present invention, the distance between the first contact end section of the first drain—drain connection layer and the first contact end section of the second drain—drain connection layer is relatively long, such that another conduction layer can be disposed in a region between them.
The present invention includes a first gate electrode layer, a second gate electrode layer, a first drain-gate connection layer and a second drain-gate connection layer. The gate electrode layers, the drain—drain connection layers and the drain-gate connection layers are located in different layers. In plan view, the first gate electrode layer and the second gate electrode layer are located between the first drain—drain connection layer and the second drain—drain connection layer. The first gate electrode layer includes a gate electrode of the first driver transistor and a gate electrode of the first load transistor. The second gate electrode layer includes a gate electrode of the second driver transistor and a gate electrode of the second load transistor. The first drain-gate connection layer connects the first drain—drain connection layer. The second gate electrode layer, and the second drain-gate connection layer connects the second drain—drain connection layer and
Kodaira Satoru
Kumagai Takashi
Noda Takafumi
Takeuchi Masahiro
Nguyen Cuong Quang
Oliff & Berridg,e PLC
Seiko Epson Corporation
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