Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-03-17

2003-05-20

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700

Reexamination Certificate

active

06567322

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-075065, filed Mar. 19, 1999; No. 11-250509, filed Sep. 3, 1999; and No. 2000-001833, filed Jan. 7, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor apparatus, and more particularly to a semiconductor memory device having a multibank structure which incorporates a redundant circuit for relieving a defect memory cell.
A semiconductor memory device has a redundant system employed to improve the manufacturing yield by substituting a redundant cell for a defect cell to relieve the defect cell when a defect cell has been detected in a portion of memory cells as a result of a test of a memory cell array. A redundant system which is employed usually at present uses a method with which one or more cell arrays including the defect cell is, as a unit, replaced with a spare element having the same size as that of the cell array (replacement of a cell array unit).
Address information of the cell array unit including the defect cell is stored in a nonvolatile memory device including fuses. Since address information is composed of a plurality of bits, a fuse set including a plurality of fuses corresponding to the plurality of bits is employed. The fuse set is usually one-to-one correspond to the spare element. Fuse sets, the number of which is the same as that of the spare elements, are provided in a chip. When the spare element is used, fuses in the fuse set corresponding to the spare element are cut in accordance with address information.
Since the redundant system requires the redundant circuit including the spare elements and the fuse sets, the area of the memory chip is enlarged excessively. Since the number of defects, which can be relieved, and the area of the redundant circuit satisfy a trade-off relationship, a variety of redundant systems substantially capable of improving the area efficiency have been suggested.
For example, a flexible redundant systems (“Faulty-Tolerant Design for 256 Mb DRAM” (refer to IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, No. 4, April 1996) suggested by Kirihata et al. is known. The foregoing method arranged such that one spare element covers a wide cell array region is able to relieve a faulty state where defect cells are eccentrically present in a portion of a chip similarly to a state where faults are present uniformly. Therefore, the number of the spare elements can be reduced, causing the area efficiency of the redundancy circuit to be improved. The foregoing method is effective in a case where the number of faults per chip has been detected or estimated.
On the other hand, a memory chip has been developed in which the memory cell array is divided into sections. For example, a memory chip is known which includes a plurality of banks arranged to simultaneously be activated.
In a memory chip of the foregoing type, the row spare element for relieving a defect memory cell in a row unit cannot be used across the bank. Therefore, a limitation is imposed such that a spare element must be prepared for each bank. As the number of the banks is enlarged, the number of sections of the memory cell array in the chip is enlarged. Hence it follows that the area of the cell array region which can be covered by one spare element is reduced.
When the spare element is provided for each bank, the possibility that defects of the memory cell eccentrically occur is raised considerably as the capacitance of the memory is enlarged. To maintain a high efficiency percentage, the number of the spare elements to be included in each bank must be enlarged. As a result, the area of the chip is enlarged excessively.
To relieve a defect cell even if defects are eccentrically present in a portion of the memory cell array in a case where the spare element can cover only a narrow region as described above, the spare element must be provided for each of the narrow cell array region. As a result, the spare elements are mounted on a chip by a number considerably larger than an average number of defects per chip. Therefore, the overall area efficiency of the chip deteriorates.
The conventional method with which the spare elements and the fuse sets are one-to-one corresponded encounters increase in the number of fuse sets as the number of the spare elements is increased. Since the fuse set generally requires an area larger than the area required for the spare element, the area efficiency of the redundant circuit excessively deteriorates.
To overcome the foregoing problem, a method is known with which the number of the fuse sets which is larger than an estimated number of defects in the overall cell array can be made to be smaller than the number of all of the spare elements. Specifically, the relationship of the corresponding information with plurality of spare row decoders in each bank is included in each fuse set. Thus, the necessity for causing each fuse set to one-to-one correspond to the spare element can be eliminated.
A portion of conventional DRAM includes a type having a structure that the overall cell array is sectioned into 16 banks. Moreover, eight spare elements are provided for each bank to cope with a state where defects are eccentrically present. Assuming that the average defects in the overall cell array is about 20, twenty eight fuse sets which is smaller than the number of all of the spare elements which is 128 are used to cope with a state where defects are uniformly dispersed or defects are present eccentrically. Since the spare elements, the total number of which is 128, are provided, the area efficiency of the spare element is unsatisfactorily low.
Note that the number of banks increases in proportion to the enlargement of the capacitance of the memory. The necessity for increasing the number of the banks is not raised in the future. The increasing rate of the number of the banks with respect to the enlargement of the capacitance of the memory will be lowered. Since the lengths of the bit line and the word line have upper limits, the size of the sub-array constituting the bank has an upper limit. Hence it follows that the number of the sub-arrays is increased. To be adaptable to the foregoing trend, a structure is employed in which when a certain bank has been activated, a sub-array belonging to the bank and maintained at a non-active state is present.
A semiconductor memory having the structure that the active sub-arrays and non-active sub-arrays belonging to the same bank are present suffers from a problem in that the area of the chip is excessively enlarged if a multiplicity of spare elements are provided for each sub-array.
Since the defect is not fined when the device is fined, a portion of defects has a relatively large width (area). Thus, use of a plurality spare elements is sometimes required.
The method with which the number of the fuse sets is made to be smaller than the total number of the spare elements involves a fact that consumption of a plurality of the spare elements causes the fuse sets to, of course, be consumed by the same number. Therefore, fewer fuse sets sustain greater damage owing to a defect having a width larger than the spare element.
FIG. 21
collectively shows defect example A and B caused from defects which are possible to occur in one bank.
The defect example A is an example in which a defect having a large area corresponding to two word lines is relieved by using one spare element. In the foregoing case, one fuse set is used.
The defect example B is an example in which two spare elements are required to relieve a defect having a large area corresponding to two word lines. In the foregoing case, two fuse sets are used.
As the device is fined, the defect example B increases. In an extreme case in which all of twenty estimated defects traverse the boundary of the unit for the substitution, insufficiency of the fuse sets occurs with reliability in spite of low possibility of insuffici

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