Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-08-15

2003-04-08

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233500

Reexamination Certificate

active

06545924

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
The present application is based on Japanese Priority Patent Application No. 2000-264358 filed on Aug. 31, 2000, the entire contents of which are hereby incorporated.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to a semiconductor memory device of DRAM type in which a self-refresh operation is constantly performed.
2. Description of the Related Art
Recently, an increased amount of data has been handled in a portable mobile terminal such as a cellular phone due to collaboration with the Internet. Nowadays, an SRAM having small power consumption is widely used in cellular phones. However, the SRAM has a disadvantage in that the SRAM has a comparatively low integration density and the cost increases as the integration density increases. In contrast, the DRAM is less expensive and has a large memory capacity. It is to be noted that the command system of the SRAM differs from that of the DRAM, so that the SRAM cannot be simply replaced by the DRAM. One of the major problems in the replacement resides in refresh control of the DRAM. The DRAM needs refresh control that constantly refreshes the memory cells in order to hold data stored therein. A constant refresh operation is enabled by externally supplying the DRAM with a refresh command. However, this applies a considerable load on a controller.
Hence, it is required that the DRAM itself periodically refreshes the memory cells (self-refresh). In the DRAM of an asynchronous type independent of clock, the refresh request internally generated may collide with an external request for an active operation (for example, a data read command or a data write command). When the refresh request leads to the read/write command from the outside of the DRAM, the read/write operation is executed after the refresh operation is completed. In contrast, when the read/write command leads to the refresh request, the refresh operation is executed after the read/write operation is completed. That is, there is no regularity between the read/write command and the refresh command, so that one of the requests that leads to the other in terms of timing is executed first.
The read/write command may be defined by a combination of control signals externally supplied (which may be called command signals). The control signals may include a chip enable signal /CE, a write enable signal /WE, and an output enable signal /OE. The read/write operation starts in synchronism with the falling edge of the chip enable signal /CE. A state transition detection signal is generated by detecting the falling edge of the chip enable signal /CE. The timing of the state transition detection signal and the timing of the refresh request internally generated are compared, and one of the signals that leads to the other is executed.
However, the conventional technique for detecting the falling edge of the chip enable signal /CE and generating the state transition detection signal causes an output delay of read data.
More specifically, the DRAM operates slower in case where consecutive read operations are applied or the read operation is executed after the write operation. The read operation is initiated in synchronism with the falling edge of the chip enable signal /ED. Hence, it is necessary to raise the chip enable signal /CE and lower it again after the read operation is completed. The read operation is delayed by the time necessary to raise the chip enable signal /CE to the high level. Similarly, the read operation after the write operation is delayed by the time necessary to raise the chip enable signal /CE to the high level.
SUMMARY OF THE INVENTION
It is a general object of the present invention to eliminate the above disadvantages.
A more specific object of the present invention is to provide a semiconductor memory device capable of outputting read data faster.
The above objects of the present invention are achieved by a semiconductor memory device having a self-refresh function comprising: a detection circuit detecting a change of an output enable signal and generating a state transition detection signal; and a decision circuit comparing the state transition detection signal and a refresh request signal internally generated and generating a signal that indicates a corresponding circuit operation.
The above objects of the present invention are achieved by a semiconductor memory device having a self-refresh function comprising: a detection circuit detecting a change of a write enable signal and generating a state transition detection signal; and a decision circuit comparing the state transition detection signal and a refresh request signal internally generated and generating a signal that indicates a corresponding circuit operation.
The above objects of the present invention are also achieved by a semiconductor memory device having a self-refresh function comprising: a detection circuit detecting a change of an output enable signal, a change of a chip enable signal, and a change of a write enable signal and generating a state transition detection signal; and a decision circuit comparing the state transition detection signal and a refresh request signal internally generated and generating a signal that indicates a corresponding circuit operation.


REFERENCES:
patent: 5075886 (1991-12-01), Isobe et al.
patent: 6256248 (2001-07-01), Leung
patent: 6275437 (2001-08-01), Kim et al.
patent: 6327210 (2001-12-01), Kuroda et al.
patent: 6392958 (2002-05-01), Lee
patent: 6396758 (2002-05-01), Ikeda et al.

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