Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-12-21

2002-12-03

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S185200, C365S207000

Reexamination Certificate

active

06490214

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-394559, filed on Dec. 26, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory circuit for setting an activation timing of a sense amplifier connected to memory cells, by using a dummy bit line sense amplifier connected to a dummy cell.
2. Related Background Art
FIG. 6
is a block diagram showing schematic configuration of a conventional semiconductor memory circuit having the dummy bit line sense amplifier
5
. The semiconductor memory device of
FIG. 6
is composed of a pair of dummy bit lines L
4
arranged in parallel to a bit line L
3
, a plurality of dummy cells
4
connected between the pair of dummy lines L
4
, and a dummy bit line sense amplifier
5
connected to one end of the dummy bit line L
4
.
Ordinary memory cells
1
are selected in units of row, when a main word line L
1
is set to high level, one of section word lines L
2
is set to high level, and one of modulated word-line address L
5
is set to high level. Each of the dummy cells
4
is usually provided by each of the section word lines L
2
.
Only one dummy cell
4
of a plurality of dummy cells
4
can be selected by a dummy cell selecting signal, and the other dummy cells
4
are constantly in non-selecting state. When the dummy cell selecting signal is in low level, data stored in the dummy cell
4
is provided to the dummy bit line
4
.
The dummy bit line sense amplifier
5
amplifiers the voltage of the dummy bit line L
4
to output the amplified output. Activation timing of the sense amplifier
2
is set by the output of the dummy bit line sense amplifier
5
.
When it is necessary to conform capacitance of the dummy bit line L
4
to capacitance of an ordinary bit line L
3
, a cell that access is impossible may be connected to the dummy bit line L
4
.
Furthermore, if a width of the dummy bit line L
4
is conformed to that of the bit line L
3
, resistance of both bit lines can be equal to each other. Moreover, if element sizes of transfer transistors and driver transistors in the dummy cell
4
are conformed to that of each transistor in the memory cell
1
, cell current flowing through both cells can be set equal to each other.
When there is provided with the dummy bit line sense amplifier
5
such as
FIG. 6
, even if processes such as a cell current, a bit line resistance or a bit line capacitance fluctuate, timing that the dummy bit line sense amplifier
5
activates the sense amplifier in accordance with the fluctuation also changes, thereby preventing malfunction. It is possible to assure timing margin for readout by arranging the dummy cell
4
at farthest location from the sense amplifier on the bit lines.
However, if there is a random dispersion on properties such as the cell current and the capacitance, the time for sensing the dummy cells
4
also fluctuates at random. According to circumstances, the timing that the dummy bit line sense amplifier
5
activates the sense amplifier may quicken. In this case, it is impossible to normally sense data read out from the memory cell
1
. In order to avoid such a problem, if sufficient margin is given to a sense start timing of the dummy cells
4
, sense time of the memory cell
1
becomes too late.
Furthermore, conventionally, because control of the dummy cell
4
had been carried out separate from that of the memory cells
1
, when the cell current of the dummy cell
4
and the timing of the dummy cell selecting signal largely changes due to the process fluctuation, data read out from the memory cell
1
may be unable to normally sense by the sense amplifier
2
or the sense timing may become too late.
SUMMARY OF THE INVENTION
A semiconductor memory circuit according to an embodiment of the present invention, comprising:
a plurality of bit lines;
memory cells connected to each of said plurality of bit lines;
sense amplifiers, each corresponding to one of said plurality of bit lines and each configured to amplify a voltage of the corresponding bit line;
dummy bit lines;
a plurality of dummy cells connected to said dummy bit lines;
a dummy sense amplifier configured to output signals with voltages obtained by amplifying the voltages of said dummy bit lines, and to set an activation timing of said sense amplifier based on the output; and
a dummy cell selecting circuit configured to simultaneously select at least two of said dummy cells, when said sense amplifier is activated.


REFERENCES:
patent: 4551820 (1985-11-01), Matsuura
patent: 4751681 (1988-06-01), Hashimoto
patent: 5317537 (1994-05-01), Shinagawa et al.
patent: 6181626 (2001-01-01), Brown
patent: 6219290 (2001-04-01), Chang et al.
patent: 6246622 (2001-06-01), Sugibayashi
patent: 0383080 (1990-01-01), None
patent: 06-176568 (1994-06-01), None
B. Amrutur, et al., “A Replica Technique for Wordline and Sense Control in Low-Power SRAM's”, IEEE Journal of Solid-State Circuits, vol. 33, No. 8, Aug. 1998, pp. 1208-1219.

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