Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1996-04-18

1998-01-13

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Bad bit

36523003, G11C 700

Patent

active

057086125

ABSTRACT:
When a test mode signal is at an inactive level, a redundant cell column control circuit selects redundant cell column select signals. When the test mode signal is at an active level, the circuit selects a predetermined bit from the column select signal to output redundant cell column selection control signals, which are supplied to redundant cell column switch circuits. In a test mode, all blocks are set to an active state to select a predetermined memory cell column, and the redundant cell columns are concurrently selected. An accelerated biassing test can be conducted for all redundant cell columns within a competent test time.

REFERENCES:
patent: 5459690 (1995-10-01), Rieger

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-331633