Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
Reexamination Certificate
2001-04-06
2002-10-22
Lebentritt, Michael S. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Fet configuration adapted for use as static memory cell
C257S314000, C257S355000, C257S368000
Reexamination Certificate
active
06469400
ABSTRACT:
Japanese patent application No. 2000-109310, filed Apr. 11, 2000, is hereby incorporated by reference in its entirety.
1. Technical Field
The present invention relates to a semiconductor memory device such as a static random access memory (SRAM).
2. Description of Related Art
An SRAM, which is one type of semiconductor memory device, does not need refreshing. Therefore, the SRAM enables system configuration to be simplified and consumes only a small amount of electric power. Because of this, the SRAM is suitably used as a memory for portable devices such as portable telephones. There has been a demand for miniaturization of portable devices equipped with the SRAM. To deal with this demand, the memory cell size of the SRAM must be reduced.
SUMMARY
An objective of certain embodiments of the present invention is to provide a semiconductor memory device capable of reducing memory cell size.
According to one embodiment of the present invention, there is provided a semiconductor memory device comprising a memory cell which is provided with a first driver transistor, a second driver transistor, a first load transistor, a second load transistor, a first transfer transistor, and a second transfer transistor, wherein:
the memory cell has a first gate electrode layer, a second gate electrode layer, a first drain-drain connecting layer, a second drain-drain connecting layer, a .first drain-gate connecting layer, a second drain-gate connecting layer, a first contact-conductive section, a second contact-conductive section, a first interlayer dielectric, and a second interlayer dielectric;
the first gate electrode layer includes a gate electrode of the first driver transistor and a gate electrode of the first load transistor;the
second gate electrode layer includes a gate electrode of the second driver transistor and a gate electrode of the second load transistor;
the first interlayer dielectric is located so as to cover the first and second gate electrode layers;
the first and second drain-drain connecting layers are located over the first interlayer dielectric;
the first and second gate electrode layers are located between the first and second drain-drain connecting layers;
the first drain-drain connecting layer is used to connect a drain region of the first driver transistor to a drain region of the first load transistor;
the second drain-drain connecting layer is used to connect a drain region of the second driver transistor to a drain region of the second load transistor;
the second interlayer dielectric is located so as to cover the first drain-drain connecting layer and the second drain-drain connecting layer;
the first and second drain-gate connecting layers are located over the second interlayer dielectric;
the first drain-gate connecting layer is used to connect the first drain-drain connecting layer to the second gate electrode layer;
the second drain-gate connecting layer is used to connect the second drain-drain connecting layer to the first gate electrode layer;
the first contact-conductive section is located in a first hole formed in a region from the first interlayer dielectric to the second interlayer dielectric;
the second contact-conductive section is located in a second hole formed in a region from the first interlayer dielectric to the second interlayer dielectric;
the first drain-gate connecting layer is connected to the second gate electrode layer with the first contact-conductive section interposed; and
the second drain-gate connecting layer is connected to the first gate electrode layer with the second contact-conductive section interposed.
According to another embodiment of the present invention, the first drain-gate connecting layer is connected to the second gate electrode layer and the second drain-gate connecting layer is connected to the first gate electrode layer without forming a contact pad layer between the first and second interlayer dielectrics. Therefore, since the first and second contact-conductive sections can be formed even if the interval between the first and second drain-drain connecting layers is decreased, the memory cell size can be reduced.
The semiconductor memory device according to another embodiment of the present invention includes gate electrode layers which become gates of inverters, drain-drain connecting layers for connecting drains of the inverters, and drain-gate connecting layers for connecting a gate of one inverter to a drain of the other inverter. In the semiconductor memory device according to another embodiment of the present invention, a flip-flop is formed by using these three layers (gate electrode layers, drain-drain connecting layers, and drain-gate connecting layers). Therefore, the pattern of each layer can be simplified (into a linear pattern, for example) in comparison with the case of forming a flip-flop using two layers. Since the pattern of each layer can be thus simplified, a semiconductor memory device with a memory cell size of 4.5 &mgr;m
2
or less can be fabricated, for example.
According to another embodiment of the present invention, the first and second gate electrode layers are located between the first and the second drain-drain connecting layers. Therefore, a source contact layer of the driver transistors can be disposed at the center of the memory cell. Moreover, a wiring in the level as the drain-drain connecting layer to which the source contact layer is connected can be disposed at the center of the memory cell. Therefore, the first and second drain-gate connecting layers can be formed more freely. This also contributes to miniaturization of the memory cell size. Note that the source contact layer is a conductive layer used to connect a source region of a driver transistor to a wiring layer.
Each of the first and second holes may have an aspect ratio of 5 or less. The first hole and the second hole with an aspect ratio of 5 or less can be easily filled with the contact-conductive sections.
Each of the first and second drain-drain connecting layers may have a thickness of 100 nm to 170 nm. This is because the first and second drain-drain connecting layers with a thickness of 100 nm or more exhibit preferable electric resistance values. If the thickness of the first and second drain-drain connecting layers is 170 nm or less, the thickness of the second interlayer dielectric does not become unduly great. This ensures that the aspect ratio of the first and second holes is 5 or less. The thickness of the first and second drain-drain connecting layers can be adjusted to 170 nm or less by allowing a high-melting-point metal nitride layer such as titanium nitride to be included in the first and second drain-drain connecting layers.
Each of the first gate electrode layer, the second gate electrode layer, the first drain-drain connecting layer and the second drain-drain connecting layer may have a linear pattern and they may be disposed in parallel. If the pattern of each layer is simple, a semiconductor memory device with a minute memory cell size can be provided.
According to another embodiment of the present invention, the memory cell may further comprise a third contact-conductive section, a fourth contact-conductive section, a first contact pad layer and a second contact pad layer;
the first contact pad layer and the second contact pad layer may respectively be located in the same level as the first drain-drain connecting layer and the second drain-drain connecting layer;
the third contact-conductive section and the fourth contact-conductive section may be located in holes formed in the first interlayer dielectric;
a source/drain region of the first transfer transistor may be connected to the first contact pad layer with the third contact-conductive section interposed; and
a source/drain region of the second transfer transistor may be connected to the second contact pad layer with the fourth contact-conductive section interposed.
If each memory cell includes the first contact pad layer, the source/drain region of the first transfer transistor can be connected to an upper wiring (bit line, for example) mo
Kodaira Satoru
Kumagai Takashi
Noda Takafumi
Takeuchi Masahiro
Lebentritt Michael S.
Menz Douglas M.
Oliff & Berridg,e PLC
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