Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-04-16

2002-10-01

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Parallel read/write

C365S233100

Reexamination Certificate

active

06459641

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor memory device which operates in synchronism with a clock signal.
BACKGROUND OF THE INVENTION
As processing speed of CPUs is enhanced, semiconductor memory devices such as a DRAM (dynamic random access memory) are required to have an increased data-transfer speed by using an increased signal frequency for input/output of data signals. SDRAMs (synchronous dynamic random access memory) are devised to meet this demand, and operate in synchronism with an input clock signal to achieve a high-operation speed.
FIG. 1
is a circuit diagram showing a portion of a DRAM with regard to peripherals of memory cells. The circuit of
FIG. 1
includes a capacitor
501
, NMOS transistors
502
through
512
, a PMOS transistor
513
, PMOS transistors
521
and
522
, and NMOS transistors
523
and
524
. The PMOS transistors
521
and
522
and the NMOS transistors
523
and
524
together form a sense amplifier
520
.
The capacitor
501
serving as a memory cell stores 1-bit information. When a sub-word-line selecting signal SW is activated, the NMOS transistor
502
serving as a cell gate opens, thereby transferring data of the capacitor
501
to a bit-line BL. When this happens, a bit-line-transfer signal BLT
1
is at a HIGH level, so that the NMOS transistors
503
and
504
are turned on. A bit-line-transfer signal BLT
0
, on the other hand, is at a LOW level, so that the NMOS transistors
505
and
506
are turned off. As a result, the data on the bit-lines BL and /BL is stored in the sense amplifier
520
via the NMOS transistors
503
and
504
. The sense amplifier
520
operates when the transistors
513
and
512
are turned on via activation of sense-amplifier-activation signals SA
1
and SA
2
, and amplifies the data of the bit-lines BL and /BL. The amplified data on the bit-lines BL and /BL is then sent to data bus DB and /DB via the NMOS transistors
510
and
511
serving as column gates when a column-line selecting signal CL is selectively activated.
In the case of data-write operations, data on the data bus DB and /DB is stored in the capacitor
501
through operation steps reversed in order with reference to the case of data-read operations.
FIG. 2
is timing charts for explaining data-read operations of the DRAM.
As shown in
FIG. 2
, when data-read operations are conducted, commands are input to the DRAM in an order of a precharge command (PRE) for precharging the bit-lines BL and /BL to a predetermined voltage level, a /RAS command (R) for a row-access operation, and a /CAS command (C) for a column-access operation.
With reference to FIG.
1
and
FIG. 2
, timing control will be described below with regard to data-read operations.
Upon input of the /RAS command, the bit-line-transfer signal BLT
0
becomes LOW (BLT
1
is HIGH), so that the bit-lines BL and /BL are connected to the sense amplifier
520
. At the same time, a precharge signal PR of
FIG. 1
is changed to LOW to end the reset conditions of the bit-lines BL and /BL. Further, a main-word-line selecting signal MW is changed to HIGH, and so is the sub-word-line selecting signal SW, thereby selecting a particular word line. This turns on the NMOS transistor
502
, so that the data of the capacitor
501
is read to the bit-line BL. As shown in
FIG. 2
, the data appears on the bit-line BL at a timing when the main-word-line selecting signal MW and the sub-word-line selecting signal SW become HIGH.
In order to drive the sense amplifier
520
, then, sense-amplifier driving signals SA
1
and SA
2
become active, thereby turning on the NMOS transistor
512
and the PMOS transistor
513
. As shown in
FIG. 2
, activation of the sense amplifier
520
results in an increase in the amplitude of data signals on the bit-lines BL and /BL.
When the amplitude of data signals is stepped up, the column-line selecting signal CL becomes HIGH in response to the /CAS command so as to select a particular column. The NMOS transistors
510
and
511
(column gates) of the selected column are turned on, so that the data is released to the data bus DB and /DB. The data on the data bus DB and /DB is output from the DRAM as a data signal DQ, and, for example, a data-read operation for consecutive four bits is conducted.
When the precharge command is input, the precharge signal PR becomes HIGH at an appropriate timing, so that the NMOS transistors
507
through
509
are turned on to precharge the bit-lines BL and /BL to a voltage VPR. This operation resets the bit-lines BL and /BL as shown in
FIG. 2
, and, thus, the DRAM is prepared for a data-read operation of a next /RAS command.
The DRAM as described above can consecutively read data from different column addresses by successively selecting different columns, and this operation is applicable when data is consecutively read from the same row address (corresponding to the same word line). The sense amplifier
520
of
FIG. 1
is provided with respect to each of a plurality of columns. The plurality of sense amplifiers
520
store data of different column addresses and the same row address. When these different column addresses are successively selected to read data from the sense amplifier
520
, therefore, consecutive data-read operations can be achieved.
When there is a need to read data from a different row address (corresponding to a different word line), however, new data needs to be read from memory cells of this word line to the bit-lines BL and /BL. Further, in order to transfer the new data to the bit-lines BL and /BL, it is required to precharge the bit-lines BL and /BL in advance. Because of this, when data is to be read from a different row address after having read data from a given row address, successive data-read timings have a large time gap therebetween as shown in FIG.
2
. In the example of
FIG. 2
, there is a gap as large as 10 clocks between successive data-read timings for different row addresses.
For the sake of explanation, a whole series of operations from the input of a row address to the output of data is divided into three steps. The first step includes command-decode operations and peripheral-circuit operations, and the second step is comprised of sense-amplifier operations. The third step relates to data-output operations. In order to achieve pipe-line operations with regard to row access, the operations of the first step are initially conducted with regard to a first row access. When the operations of the second step start with regard to the first row access, a second row access begins the operations of the first step. Further, when the first row access starts the operations of the third step, the operations of the second step are conducted with regard to the second row access, and, also, the operations of the first step should start with regard to a third row access. In this manner, row-access pipe-line operations can be achieved if the operations of the first, second, and third steps are performed in parallel with respect to different row accesses.
In conventional DRAMs, however, a burst length can be set to different lengths when a plurality of column addresses are consecutively read at the same row address. That is, the number of data pieces subjected to consecutive data-read operations is defined by a specified burst length, and a corresponding number of data pieces, as indicated by the specified burst length, are read from consecutive column addresses. In this case, an operation period of the sense-amplifier operations at the second step, i.e., a period during which the sense amplifiers are operating to allow accesses to be made to consecutive column addresses, is subject to a change, depending on a burst length which is determined by a mode setting.
Since the operation period of the second step is subject to a change dependent on a mode setting, it is impossible to carry out undisturbed pipe-line operations with regard to row accesses. Namely, when situations are viewed from the side of a memory controller, the memory cont

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