Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-12-27

2002-06-04

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S063000

Reexamination Certificate

active

06400628

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Background Art
A memory cell array of a DRAM (Dynamic Random Access Memory) has a configuration in which memory cells, each including a transistor and a capacitor, are arranged in array-like manner, i.e. in row and column directions. In its operation, a word line selected by a row address rises to turn on the transistor connected to the word line. Each potential stored in the capacitor of a memory cell arranged in a certain row is thereby read out simultaneously by a sense amplifier via a bit line, and is amplified to the level “H” (array voltage, VDD) or “L” (VSS). The above-described bit line is pre-charged to a bit line pre-charge voltage, i.e. a constant voltage (VBL, generally VDD/2), until the above-described word line rises. A cell plate electrode is arranged as a common opposing electrode for a capacitor of each memory cell, and is fixed to a constant cell plate voltage (VCP, generally VDD/2).
In case of a DRAM having a large capacity, in order to accommodate with the increase of power consumption and access time, the memory cell array is divided into a large number of sub memory arrays and the word line is formed to have a hierarchical word configuration including a main word line and a sub word line.
FIG. 6
schematically shows a configuration of a multi-divided memory array and
FIG. 7
is a detailed view of a sub memory array SMA, a sub word driver band SWD and a sense amplifier band SA.
Mainly referring to
FIG. 6
, in the multi-divided memory array, the memory cell array is divided into a large number of sub memory arrays SMA, and the sub word driver band SWD and the sense amplifier band SA are arranged for each of the plurality of sub memory arrays SMA. A main word line MWL extends in row direction crossing over the plurality of sub memory arrays SMA arranged in row direction, and a sub word line SWL connected to the main word line MWL via the sub word driver SWD also extends in row direction across each of the sub memory arrays SMA. The main word line MWL is driven by a main word driver MWD in response to the signals of a row decoder RD.
Mainly referring to
FIG. 7
, the sub memory array SMA has a plurality of memory cells MC arranged in a matrix. Each gate of the memory cells MC arranged in the same row is connected to the sub word line SWL, which is in turn connected to each of the drivers SWDa of the sub word driver band SWD. The memory cells MC arranged in the same column are respectively connected to one of a pair of bit lines BL and /BL. The bit-line pair BL and /BL is connected to any of the sense amplifiers S/A, illustrated at the top or the bottom in
FIG. 7
, via NMOS transistors NT
10
and NT
11
in which a shared gate signal SHRb is input to the respective gates.
In addition to a plurality of sense amplifiers S/A and a plurality of S/A shared circuits including NMOS transistors NT
10
to NT
13
, the sense amplifier band SA has a plurality of equalizing circuits including NMOS transistors NT
15
to NT
17
. These equalizing circuits are used to apply the pre-charge voltage VBL described above to the bit lines BL and /BL.
The sub word line SWL is driven by the sub word driver SWDa in response to the signals of the main word line MWL and a sub decoding line SDL.
The above-described memory cell MC has a one transistor-one capacitor configuration including a transistor
110
and a capacitor
120
, as shown in
FIG. 8
, for example. As shown in
FIG. 7
, a cell plate
113
of capacitor
120
extends substantially over entire region of the sub memory array SMA. Cell plate
113
is connected, at several portions, to a VCP power-supply interconnection
117
a
extending in the vicinity of the border between the sub memory array SMA and the sub word driver band SWD, so that cell plate
113
is fixed to the cell plate voltage VCP.
An example of a conventional configuration for applying the cell plate voltage VCP to the cell plate is shown in FIG.
9
.
Referring to
FIG. 9
, MOS transistors
110
and
130
are formed on the surface of a semiconductor substrate
101
electrically isolated by a trench isolation
102
. MOS transistors
110
and
130
have pairs of source/drain regions
103
and
121
respectively, and the transistors have respective gate electrodes
105
and
123
formed on the regions sandwiched between the source/drain regions
103
and
121
, with gate insulating layers
104
and
122
interposed, respectively. In particular, gate electrode
105
forms the sub word line SWL described above.
A bit line
107
and dummy bit lines
107
a
,
107
b
are formed on an interlayer insulating layer
106
covering MOS transistors
110
and
130
. Bit line
107
is electrically connected to source/drain region
103
through a contact hole
106
a.
A COB (Capacitor Over Bitline) structure is employed in that a capacitor
120
is formed on an interlayer insulating film
108
covering bit line
107
. Capacitor
120
is a stacked capacitor having a storage node
111
and a cell plate
113
opposing to storage node
111
with a capacitor dielectric layer
112
posed therebetween. Storage node
111
has a tubular portion extending upward and is electrically connected to source/drain region
103
through a contact hole
108
a.
A dummy storage node
111
a
is formed in a dummy region. A main word line
115
and an intermediate interconnection
115
a
are formed as the first metal interconnections on an interlayer insulating film
114
covering capacitor
120
. Intermediate interconnection
115
a
is electrically connected to cell plate
113
through a contact hole
114
a.
A VCP power-supply interconnection
117
a
and an interconnection
117
b
are formed as the second metal interconnections on an interlayer insulating film
116
covering main word line
115
and intermediate interconnection
115
a
. VCP power-supply interconnection
117
a
is electrically connected to intermediate interconnection
115
a
via a through hole
116
a
. A power-supply interconnection, a GND interconnection and a global I/O interconnection are also formed as the second metal interconnections.
Thus, the feeding of the cell plate voltage VCP to the cell plate
113
has conventionally been provided from VCP power-source line
117
a
through intermediate interconnection
115
a.
As can be seen from
FIG. 7
, cell plate
113
having a large area approximately the same as the sub memory array is fed at several portions with the VCP power supply, whereby the potential is surely fixed. Insufficient fixation of the potential causes the variation of the potential of cell plate
113
upon continued writing of the same data in page mode operation, and the insufficient storage potential of the memory cell MC. “L” to “H” error tends to occur as the potential of cell plate
113
is raised, whereas “H” to “L” error tends to occur as the potential is lowered.
Although it has been described that VCP power-source line
117
a
is arranged on the border between the sub memory array region and the sub word driver band, it may also be arranged on the sub memory array region. In any case, by arranging VCP power-source line
117
a
in a region other than the sub word driver band, the increase in the width of the sub word driver band is prevented.
However, in the system LSI (Large Scale Integrated) circuit embedding DRAM, the method of feeding VCP to the above-described cell plate may not be used in some cases, as will be described in the following.
When the memory array is configured with the memory cells of the stacked-capacitor type, a large step is generated between the memory array portion and the other peripheral portion. Further, as shown in
FIG. 9
, the step in the interlayer insulating film
116
of an upper layer is larger than that in interlayer insulating film
114
of a lower layer. The height of the step of interlayer insulating film
116
could be 100 nm or more depending on the height of the stacked capacitor.
On the other hand, when forming a plurality

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