Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-10-18

2002-06-04

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230010

Reexamination Certificate

active

06400637

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor memory device and more particularly relates to a semiconductor memory device with a hierarchical word line structure.
BACKGROUND ART
In recent years, a hierarchical word line structure has been adopted by high-speed, high-density DRAMs (dynamic random access memories) to relax interconnect line pitch limitations. This is a structure in which each word line is made up of a main word line and sub-word lines, which respectively belong to two different layers. One such example is a DRAM disclosed in Japanese Laid-Open Publication No. 6-195964 (published on Jul. 15, 1994). T. Sugibayashi et al. showed an exemplary DRAM using non-multiplexed address input in “A 30 ns 256 Mb DRAM with Multi-Divided Array Structure”, ISSCC, Digest of Technical Papers, pp. 50-51, February 1993. In these prior art examples, only part of sub-word lines associated with a common main word line are activated.
In the prior art, however, even in activating multiple sub-word lines associated with a single main word line either sequentially or randomly, a sequence consisting of (1) activating the main word line, (2) activating a sub-word line, (3) deactivating the sub-word line and (4) deactivating the main word line is repeatedly performed. Accordingly, every time sub-word lines to be activated are changed, a main word line needs to be re-selected, thus interfering with increase of row access speeds.
DISCLOSURE OF INVENTION
An object of the present invention is to increase the row access speeds of a semiconductor memory device with a hierarchical word line structure.
To achieve this object, the present invention adopts a construction including first means for activating a main word line and second means for changing activated ones of sub-word lines, which are associated with the main word line in common, while the main word line is being activated. If multiple sub-word lines, associated with a single main word line in common, should be activated either sequentially or randomly using this structure, the sub-word lines to be activated can be changed with the same main word line still selected. Thus, the row access speeds increase compared to the known structure. Preferably, a structure in which the second means is operated only when a particular mode is specified by a given control packet, is employed.


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English translation of the International Preliminary Examination Report dated Nov. 21, 2000.

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