Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-06-15

2002-12-31

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Multiple port access

C365S222000, C365S189011

Reexamination Certificate

active

06501701

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device.
FIG. 2
is a circuit diagram illustrating an array
200
of dynamic random-access memory (DRAM) cells
100
, each including two transistors
110
a
and
101
b
and one capacitor
102
, and its peripheral circuits for a known semiconductor memory device. In each of the memory cells
100
shown in
FIG. 2
, the first transistor
110
a
has its gate, drain and source connected to first word line WL
1
a
, first bit line BL
1
a
and storage node SN, respectively. The second transistor
101
b
has its gate, drain and source connected to second word line WL
1
b
, second bit line BL
1
b
and storage node SN, respectively. One of the two electrodes of the capacitor
102
is connected to the storage node SN, while the other electrode thereof is used as a cell plate.
Thus, each memory cell
100
includes two transistors
101
a
and
101
b
that are independently controllable with respect to one capacitor
102
. Accordingly, the same memory cell
100
can be accessed through two different ports, i.e., a port including the first word line WL
1
a
, first transistor
101
a
and first bit line BL
1
a
and a port including the second word line WL
1
b
, second transistor
101
b
and second bit line BL
1
b
. In other words, a memory cell
100
of this type realizes interleaved access.
A memory cell
100
of this type will be herein called a “2Tr1C memory cell”. Also, the port accessing a memory cell
100
by way of the first transistor
101
a
will be herein called an “A-port” while the port accessing the same memory cell
100
by way of the second transistor
101
b
will be herein called a “B-port”.
A synchronous DRAM (SDRAM) using normal memory cells, each including one transistor and one capacitor, has multiple banks and can transfer input or output data continuously by performing an interleaved operation between or among those banks. However, where multiple memory cells belonging to the same bank should be accessed successively, the SDRAM needs a precharge/equalize interval. Accordingly, the transfer of data should be stopped for this interval.
On the other hand, a semiconductor memory device including the 2Tr1C memory cells
100
performs a burst mode operation using one of the two ports while the other port is in standby mode. Accordingly, the device can perform a precharge operation using the latter port. In addition, if a command is input in view of the length of burst data and the latency of data transferred, then the device can consecutively input or output data to/from even multiple memory cells belonging to the same bank.
FIG. 6
is a timing diagram illustrating how the semiconductor memory device including the 2Tr1C memory cells
100
reads out burst data. Suppose this memory device inputs addresses by a non-multiplexer method and has a latency of 2, a random-access cycle number of 4 and a burst length of 4. In the example illustrated in
FIG. 6
, the first and second types of word lines activated are identified by WLa and WLb, respectively.
As shown in
FIG. 6
, a read command RD is input at a time T
1
. In response, the first word line WL
1
a
, for example, is activated and data is read out through the A-port including the first bit lines BL
1
a
, BL
3
a
, BL
5
a
and so on. As a result, data bits Da
0
through Da
3
are output consecutively between times T
3
and T
7
.
At a time T
5
when a next command can be input, a read command RD is input again. In response, the second word line WL
1
b
, for example, is activated and data is read out through the B-port including the second bit lines BL
1
b
, BL
3
b
, BL
5
b
and so on. As a result, data bits Db
0
through Db
3
are output consecutively between times T
7
and T
11
.
The second bit lines BL
1
b
and so on, included in the B-port, are precharged and equalized while the data is read out through the A-port. Accordingly, as soon as the burst data has been read out through the A-port, the data can be read out through the B-port. In this manner, data can be transferred continuously.
Thus, while the memory device is precharging using one of the ports, the device can access the memory cells
100
through the other port. As a result, this memory device requires no apparent precharge interval and can perform read and write operations at a high speed.
Even a semiconductor memory device with these two ports also needs a refresh operation. Normally, the refresh operation should be performed while no memory cells are accessed (i.e., no data is read out or written from/on any memory cells). Thus, it has been necessary to design a system with the refresh timings taken into account or to suspend the data input/output operation for the refresh interval. As a result, the system might have had its configuration overly complicated. Furthermore, the refresh operation might also prevent the user from taking full advantage of the performance a chip originally has.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to enable a semiconductor memory device to transfer data continuously without stopping its read or write operation for the purpose of refreshing.
Specifically, a semiconductor memory device according to the present invention includes memory array, first and second rows of sense amplifiers and selector. The memory array has first and second ports. The first and second rows are associated with the first and second ports, respectively. Responsive to a port selection signal, the selector selects the first or second port to transfer burst data therethrough, and couples the first or second row, associated with the port selected, to a data input or output circuit. If the selector has selected the first port, the device performs a refresh operation on the memory array using the second row while transferring the burst data through the first port. On the other hand, if the selector has selected the second port, the device performs the refresh operation on the memory array using the first row while transferring the burst data through the second port.
According to the present invention, while the memory device is transferring burst data through one of the two ports, the device can perform a refresh operation using the other port. Thus, there is no need to stop the data transfer for the refreshing purposes and the burst data can be transferred continuously at a high speed.
In one embodiment of the present invention, the memory device preferably further includes a command generator for generating the port selection signal on receiving a read or write command. Then, every time the memory device receives a read or write command, the device can transfer the burst data through one of the two ports that has just gone through the refresh operation.
In this particular embodiment, the memory device preferably further includes a refresh timer and a refresh control circuit. The refresh timer preferably outputs a refresh request signal. On receiving the read or write command, the command generator preferably generates a command detection signal. In response to the refresh request signal and the command detection signal, the refresh control circuit preferably generates a refresh command to refresh the memory array. Then, there is no need to control the refresh timings externally.
Specifically, the refresh control circuit preferably includes means for setting a refresh enabled interval and a refresh controller. The setting means generates a refresh enable signal, indicating an interval during which the refresh operation is enabled, in response to the command detection signal. The refresh controller generates the refresh command in response to the refresh enable signal and the refresh request signal. Then, no refresh commands will be generated in an interval in which the refresh operation is disabled.
In this case, the memory device preferably transfers the burst data of a predetermined burst length through either the first or second port selected on receiving the read or write command.
More specifically, the setting means preferably includes a counter

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