Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-04-17

2002-11-12

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S303000, C257S306000, C257S903000

Reexamination Certificate

active

06479860

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to SRAM (Static Random Access Memory) provided with memory cells each including 6 MOS (Metal Oxide Semiconductor) transistors (hereinafter referred to as full-CMOS cell) and a fabrication process therefor, and more particularly, to a structure of a SRAM memory cell capable of improving soft error resistance and a fabrication process therefor.
2. Description of the Background Art
In company with development toward a lower operating voltage in SRAM devices, the main stream in 3 volt or less applications, a few years ago, had been SRAMs with memory cells including 4 MOS transistors of a high resistance load type or a TFT load type and two loads.
However, with further progress in reduced operating voltage such as 2.5 V, 1.8 V and to 1.5 V in recent years, a need for SRAM devices of a high resistance load type or a TFT load type have been on the decline because of its poor operating characteristics and instead, the dominant place has been being occupied by SRAMs having full-CMOS cells each including 6 MOS transistors.
Note that the term “full-CMOS cell” generally means a memory cell constructed of 2 bulk access n MOS transistors, 2 bulk driver n MOS transistors and 2 bulk load p MOS transistors.
A full-CMOS cell is superior to an SRAM cell of a high resistance load type or a TFT load type, both having storage nodes of a low charging ability, in regard to soft error resistance since in the full-CMOS cell, a storage node on the H (high) side of a bulk p MOS transistor can be charged. Note that soft errors are a phenomenon that &agr; particle radiation emitted from radioactive impurities such as U or Th present in trace levels in common semiconductor packaging substances passes through a silicon substrate, and thereby, electron-hole pairs are generated in the bulk of the substrate and the information state of a cell is upset by noise of generated electron-hole pairs, leading to malfunction of the memory.
With progressive reduction in design rules, a cell size of SRAM memory has been smaller year by year and the trend toward lower operating voltage has also been enhanced. Along with such circumstances in change, a stored electric charge (voltage x capacitance) of a storage node of a SRAM memory cell has been on the decrease, which produces a soft error problem even in a full-CMOS cell.
For this reason, there has arisen a necessity to develop a method of protecting memory cells from soft errors even in a case of a full-CMOS cell, especially of a low operating voltage type adopting fine design rules of 0.18 &mgr;m or less.
An example of a full-CMOS cell to which a capacitance is added for reducing a soft error rate is disclosed in U.S. Pat. No. 5,541,427, wherein a capacitance is formed on an interconnect connecting storage nodes therebetween.
In order to obtain the above described capacitance, in U.S. Pat. No. 5,541,427 an insulating layer and a metal layer such as of tungsten are formed on an interconnect connecting storage nodes therebetween. The insulating layer and the metal layer are patterned using respective different masks. Therefore, a case arises where a capacitance decreases and cannot be ensured to a desired level, due to poor registration between masks in fabrication process for the insulating layer and the metal layer.
SUMMARY OF THE INVENTION
The present invention has been made in order to solve the above problem. It is accordingly an object of the present invention is to reduce a variation in capacitance added to a storage node of a semiconductor memory device.
A semiconductor memory device includes: memory cells each having first and second access MOS transistors, first and second driver MOS transistors and first and second load MOS transistors; a first gate forming a gate of the first driver MOS transistor and a gate of the first load transistor; a first conductive layer, formed on the first gate with a first insulating layer interposing therebetween, and for forming a capacitance between the first gate and the first conductive layer; a second gate forming a gate of the second driver MOS transistor and a gate of the second load MOS transistor; a second conductive layer, formed on the second gate with a second insulating layer interposing therebetween, and for forming a capacitance between the second gate and the second conductive layer; a first local interconnect connecting the first gate and the second conductive layer therebetween; and a second local interconnect connecting the second gate and the first conductive layer therebetween.
By forming the insulating layers and the conductive layers on the first and second gates in such a way, capacitors can be formed on the first and second gates. Herein, by connecting the first gate and the second conductive layer therebetween using the first local interconnect, and connecting the second gate and the first conductive layer therebetween using the second local interconnect, capacitances of the respective capacitors can be added to a storage node. Furthermore, with the capacitors formed on the first and second gates, respectively, a group of the first conductive layer, the first insulating layer and the first gate and a group of the second conductive layer, the second insulating layer and the second gate can be patterned using respective common masks. With the common masks employed, a prescribed overlapping area between layers can be ensured, whereby a variation in capacitance added to a storage node can be reduced.
A semiconductor memory device of the present invention includes: word lines; and a first well region of a first conductivity type, a second well region of a second conductivity type and a third well region of the first conductivity type, the three being arranged in each memory cell in an extending direction of each word line, wherein the first access MOS transistor and the first driver MOS transistor are formed in the first well, the first and second load MOS transistors are formed in the second well region and the second access MOS transistor and the second driver MOS transistor are formed in the third well region.
By adopting a layout as described above, a layout of an active layer and a gate can be made to assume a simple shape close to a straight line and a memory cell area can be reduced. Accordingly, a variation in capacitance added to a storage node can be decreased while down-sizing a memory cell area.
The first and second gates and the first and second conductive layers each preferably include a polysilicon layer. In this case, the first and second insulating layers are each formed between polysilicon layers.
By adopting such a construction and process, the fabrication process for DRAM (Dynamic Random Access Memory) which has been established based on proven historical records can be applied in a fabrication process for semiconductor memory devices of the present invention, which allows for easy formation of a large capacitance in a small area.
The first and second conductive layers each may be of a structure including a polysilicon layer and a silicide layer formed on the polysilicon layer. Alternatively, the first and second conductive layers each may be of a structure including a layer including metal. By adopting such structures, the first and second conductive layers can be of a low resistance.
The first and second access MOS transistors have respective gates formed by directly stacking an upper conductive layer corresponding to the first and second conductive layer on a lower conductive layer corresponding to the first and second gate.
With such a structure, it is prevented from occurring that the gates of the first and second access MOS transistors are added with respective unnecessary capacitances while lowering resistances of the gates of the first and second access MOS transistors. That is, there arises no necessity to adopt a special method by which the first and second transistors are operated with coupling capacitances.
A semiconductor memory device of the present invention includes: a memory cell region in w

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