Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-11-19

2002-12-17

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000

Reexamination Certificate

active

06496429

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a redundancy circuit for repairing a failure in normal memory cells by replacement. More particularly, the invention relates to a configuration for shortening a test time of a semiconductor memory device having a defect repaired by performing a replacement on an internal data line (IO line) basis.
2. Description of the Background Art
FIG. 18
is a diagram schematically showing the configuration of an array portion of a conventional semiconductor memory device. In
FIG. 18
, the semiconductor memory device includes a memory mat MM divided into a plurality of IO unit blocks IBO to IBn along the row direction, a row/column decoder band RCB for selecting a memory cell in memory mat MM, and a data path DPH for transmitting/receiving data to/from the selected memory cell in memory mat MM. In each of IO unit blocks IBO to IBn, memory cells of 32 bits are simultaneously selected at the time of column selection. For the memory cells (
32
IO) of 32 bits simultaneously selected, a spare memory array and a spare IO line pair SIO for repairing a defective memory cell column are provided. To the spare IO line pair, spare memory cells in the spare memory array are coupled. In each of the IO unit blocks IBO to IBn, in defective column repairing, a defective column is repaired by replacing the corresponding internal data line pair (IO line pair) with the spare IO line pair.
In row/column decoder band RCB, a row decoder for selecting a row of memory cells in memory mat MM, and a column decoder for selecting a column of the memory cells in memory mat MM are aligned. As will be described in detail later, a word line for transmitting a row selection signal from the row decoder and a column selection line for transmitting a column selection signal from the column decoder are disposed in parallel with each other in the row direction.
Data path DPH includes a circuit for inputting/outputting data between the semiconductor memory device and an outside of the semiconductor, an input buffer and a write driver for writing data, a preamplifier and an output buffer for reading data, and a spare replacement circuit for replacing a defective column with an IO line pair to repair the defective column.
In the semiconductor memory device shown in
FIG. 18
, replacement with a spare IO line for repairing a defective column is executed on the IO unit block basis (IBO to IBn). Specifically, in each of IO unit blocks IB
0
to IBn, normal memory cells and spare memory cells for repairing a defective normal memory cell are disposed.
FIG. 19
is a diagram schematically showing the configuration of IO unit block IB
0
illustrated in FIG.
18
. Since IO unit blocks IB
0
to IBn have the same configuration, in
FIG. 19
, IO unit block IB
0
is representatively shown. In
FIG. 19
, IO unit block IB
0
is divided into a plurality of row blocks RB#
0
to RB#
15
along the column direction. Each of row blocks RB#
0
to RB#
15
is divided into a plurality of unit memory arrays UMA along the row direction. By unit memory arrays UMA aligned in the column direction, a column block CB# is formed. In
FIG. 19
, each of row blocks RB#
0
to RB#
15
is divided into 33 unit memory arrays UMAs. As column blocks CB#, therefore, 32 column blocks CB#
0
to CB#
31
and a spare column block SCB#
0
are disposed.
In correspondence with column blocks CB#
0
to CB#
31
, internal data line pairs (global data line pairs) GIO
0
to GIO
31
are disposed, respectively. For spare column block SCB#
0
, a spare internal data line pair (spare global data line pair) SGIO
0
is disposed. In unit memory array UMA, memory cells are arranged in rows and columns. A row block RB# is selected by the row decoder in the row/column decoder band, and column selection is performed on the unit memory array in the selected row block by the column decoder disposed for the selected row block.
Global data line pairs GIO
0
to GIO
31
and spare global data line pair SGIO
0
are shared by the unit memory arrays UMA included in column blocks CB#
0
to CB#
31
and spare column block SCB#
0
, respectively. One row block is selected, column selection is performed in the selected row block, and data in the memory cells of 33 bits including a spare memory cell data is transferred. In a row block RB#, the normal and spare memory cells are simultaneously selected and coupled to global data line pairs GIO
0
to GIO
31
and spare global data line pair SGIO
0
.
FIG. 20
is a diagram showing the configuration of IO unit block IBO more specifically. Each of the other IO unit blocks IB
1
to IBn has a similar configuration. In
FIG. 20
, in IO unit block IBO, unit memory arrays UMA are arranged in 16 rows and 33 columns. Unit memory array UMA has memory cells arranged in 256 rows and 16 columns. In row blocks RB#
0
to RB#
15
, spare word lines SWL
0
to SWL
15
are disposed, respectively. A defective memory cell row is repaired on a row block basis.
In row block RB#
0
, word lines WL
0
to WL
255
and spare word line SWL
0
are disposed being shared by corresponding 33 unit memory arrays UMA. Column selection lines CSL
0
to CSL
15
are disposed being shared by 33 unit memory arrays UMA.
In row block RB#
1
, word lines WL
256
to WL
511
and spare word line SWL
1
are disposed, and column selection lines CSL
16
to CSL
31
are disposed in the row direction.
In row block RB#
15
, word lines WL
3840
to WL
4095
, spare word line SWL
15
, and column selection lines CSL
240
to CSL
255
are provided in the row direction and shared by unit memory arrays UMA in row block RB#
15
.
In each of row blocks RB#
0
to RB#
15
, word lines, spare word line, and column selection lines CSL are provided being shared by corresponding unit memory arrays UMA. In memory cell selection, consequently, selection of memory cell row and column is executed also in spare column block SCB#
0
. In each of unit memory arrays UMA, according to a 1/16 decoding operation, one of 16 columns is selected and coupled to the corresponding global data line GIO (in GIO
0
to GI
031
). Simultaneously, in spare column block SB#
0
as well, a spare memory cell column is selected and coupled to spare global data line pair SGIO
0
.
Spare column block SCB#
0
is used to repair a defective column on the row block basis in IO unit block IB
0
or replace a defective global data line pair GIO. Without waiting for a result of determination whether a defective column address is designated or not, normal memory cells and spare memory cells are simultaneously selected. After the spare determination, when a defective column address is designated, the corresponding defective global data line pair GIO is replaced by the spare global data line pair SGIO
0
. By performing a column selecting operation before the spare determination, time for accessing a column (writing/reading of data) is shortened.
FIG. 21
is a diagram schematically showing an example of the configuration of a unit memory array UMA. In
FIG. 21
, unit memory array UMA includes normal memory cells NMC disposed in plural rows and plural columns (256 rows and 16 columns) and spare memory cells SMC aligned in a row. Normal memory cells NMC and spare memory cells SMC are aligned in the column direction.
Word lines WL are disposed in correspondence with the rows of normal memory cells NMC. In unit memory array UMA, 256 word lines are disposed. In
FIG. 21
, word lines WL
0
to WL
255
are disposed. To each of normal word lines WL
0
to WL
255
, memory cells in the corresponding row are connected. To spare word line SW
0
, spare memory cells SMC are coupled. Normal memory cells NMC and spare memory cell SMC are aligned in each column, and bit line pairs BLP
0
to BLP
15
are disposed in correspondence with the memory cell columns. Each of bit line pairs BLP
0
to BLP
15
consists of bit

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