Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-08-31

2002-11-19

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S051000, C365S063000, C365S226000

Reexamination Certificate

active

06483763

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device such as a dynamic random access memory (DRAM), and more specifically to an improved sense amplifier drive circuit thereof.
In general, a DRAM stores a small electric charge in a section referred to as a memory cell, and holds an electric charge as data of logic “1” or data of logic “0”. The memory cells are arranged in an array. Any memory cell can be selected by inputting a row address and a column address externally. The row address is decoded by a row decoder to select any bit line pair, whereas the column address is decoded by a column decoder to select any word line. The memory cell is located at each intersecting point of the word lines and the bit lines.
In a data read-out operation, an arbitrary word line is activated, whereby data with a small electric charge in all the memory cells connected to the word line are read out in respective bit lines connected to the memory cells, and amplified by sense amplifiers connected to the bit lines. To amplify the data with a sense amplifier, two bit lines, i.e., a bit line pair is required because a potential of a bit line in which data is not read out is used as a reference potential.
A read-out operation includes the operations of selecting any bit line pair from a plurality of bit line pairs for which an amplifying operation has been performed by a sense amplifier, extracting data from the selected bit line pair into a global data line, further amplifying the data with a main amplifier and transmitting the data to the outside of the DRAM through an interface.
The present invention is directed, in particular, to a drive circuit of the sense amplifier, among the elements constituting a DRAM.
A typical example of a conventional sense amplifier drive circuit will be described with reference to FIG.
6
. In
FIG. 6
, MA is a memory array that has multiple memory cells MC arranged in an array. WL is a word line, and BL
106
and /BL
107
are bit lines. SA
101
is a CMOS sense amplifier that has an NMOS amplifier
108
having two NMOS transistors N
1
and N
2
, and a PMOS amplifier
109
having two PMOS transistors P
1
and P
2
. QSDN
102
is an NMOS sense amplifier drive transistor, which turns on when it receives a sense amplifier activating signal SAN at the gate thereof and connects a grounding power line VSS to the source of the NMOS amplifier
108
. QSDP
103
is a PMOS sense amplifier drive transistor, which turns on when it receives a sense amplifier activating signal SAP at the gate thereof and connects a power line VDD of a predetermined potential to the source of the PMOS amplifier
109
. Both reference numerals
104
and
105
are sense amplifier driving lines, each of which has a wiring resistance r. A plurality of CMOS sense amplifiers SA are connected in parallel to these sense amplifier driving lines
4
and
5
. Hereinafter, the operations of the sense amplifier drive circuit will be described briefly.
When a word line WL is activated, a small potential of a memory cell MC connected to the word line WL is read out in one bit line of a bit line pair consisting of the bit lines BL
106
and /BL
107
that are precharged to the midpoint potential (potential that is a half of a predetermined potential of the power line VDD). Then, when the sense amplifier drive transistors QSDN
102
and QSDP
103
are turned on by the sense amplifier activating signals SAN and SAP, respectively, the sensing operation starts in the sense amplifier SA. By means of this operation, the other bit line of the bit line pair is charged to a predetermined potential by the PMOS sense amplifier drive transistor QSDP
103
, whereas the other bit line is discharged to a ground potential by the NMOS sense amplifier drive transistor QSDN
102
. By means of this operation, a small potential of a memory cell MC can be amplified. Furthermore, in this amplifying operation, the charging current flows into the sense amplifier driving line
105
and the discharging current flows into the sense amplifier driving line
104
.
However, in the conventional sense amplifier drive circuits having a configuration in which the charging or the discharging current from multiple sense amplifiers SA
101
concentrates on one sense amplifier driving line
104
or
105
, a significant voltage drop occurs because of the wiring resistance r of the sense amplifier driving lines
104
and
105
themselves, and it takes a long time to charge and discharge the bit lines BL
106
and /BL
107
. As a result, the data readout speed may be reduced, or data may not be read out correctly.
A cause of this problem will be described by taking the operation of the NMOS amplifier
108
side as an example. (Herein, since the PMOS amplifier
109
side is symmetrical to the NMOS amplifier
108
side with regard to the principle of the operation, description thereof will be omitted.) When a word line WL is activated and a small potential is read out from an arbitrary memory cell MC of the memory cell array MA into one bit line of a bit line pair (e.g., BL
106
), then sense amplifier activating signals SAP and SAN allow the sense amplifier drive transistors QSDN
102
and QSDP
103
to turn on, respectively, so as to activate a sense amplifier SA
101
, and the amplifying operation starts.
At this time, when the PMOS amplifier
109
turns on and the potential of the bit line BL
106
increases, the gate potential of the NMOS transistor N
2
of the NMOS amplifier
108
connected to the bit line BL
106
increases. Therefore the impedance of the NMOS transistor N
2
becomes low and allows more current to flow therethrough. As a result, when the current flowing from the other bit line /BL
107
that makes a pair with the bit line BL
106
into the sense amplifier driving line
104
, i.e., the discharging current becomes higher than the current capacity of the sense amplifier drive transistor QSDN
102
, or when a voltage drop caused by the wiring resistance r of the sense amplifier driving line
104
is significant, a source potential (bottom potential) of the NMOS amplifier
108
rises and floats. Accordingly, a voltage Vgs between the gate and the source of the NMOS transistor N
2
of the NMOS amplifier
108
becomes low, and therefore, the current capacity of the NMOS transistor N
2
drops and it takes a long time to discharge. As a result, the data amplifying operation takes longer time and the read-out speed is reduced, and thus the data can not be read out correctly.
Furthermore, when some transistors among the NMOS transistors N
1
and N
2
of the sense amplifier SA
101
have a higher threshold voltage due to non-uniformity during the manufacturing process, it becomes more difficult for these NMOS transistors to be ensured the threshold voltage because of the increase of the source potential. Therefore, the operation of turning the NMOS transistor on becomes even slower and the data read-out speed is reduced more significantly.
The reduction in the read-out speed due to floating of the source potential of the NMOS amplifier
108
can occur in the following cases. For example, the read-out speed depends on the pattern of data to be read out (which indicates in the read-out operation what data is read out in each of the multiple bit line pairs that are subjected to the read-out operation), and the speed at which the sensing operation is performed varies depending on the pattern. The pattern resulting in the lowest operation speed is to read out “0” from one bit line pair and data “1” from all of the remaining bit line pairs. More specifically, the bit line from which “1” is read out has a precharge potential+.V of a small voltage at the beginning of the amplifying operation. This voltage provides the gate potential for one of the NMOS transistors N
1
and N
2
of the sense amplifier, and discharge is performed by this transistor. On the other hand, in the bit line pair from which “0” is read out, discharge is performed by the transistor having the gate provided with the precharge potential serving as a reference pote

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