Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-04-27

2002-11-26

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000

Reexamination Certificate

active

06487104

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims benefit of priority under 35USC §119 to Japanese Patent Application No. 2000-137098, filed on May 10, 2000, the contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of The Invention
The present invention relates generally to a semiconductor memory device. More specifically, the invention relates to a ferroelectric memory for storing data in a nonvolatile manner using a memory cell comprising a ferroelectric capacitor and a transistor.
2. Description of Related Art
At present, semiconductor memories are utilized in many fields, such as main memories of large computers, personal computers, various appliances and portable telephones. As semiconductor memories, volatile DRAMS and SRAMs, and non-volatile mask ROMs and EEPROMs are on the market. In particular, DRMMs are excellent in respect of low costs and high speed performance in spite of the volatile, and occupy most of the memory market. EEPROM flash memories, which are electrically rewritable non-volatile memories, are not on the market as much as DRAMs since there are disadvantages in that the number of rewriting operations are limited to about 10
6
, that a writing time of micro seconds is required and that a high voltage is required for carrying out a writing operation.
On the other hand, ferroelectric memories (ferroelectric RAMs) using ferroelectric capacitors are widely noticed as non-volatile memories having high speed performance since they were proposed in 1980. That is, ferroelectric memories have advantages in that they store binary data in a nonvolatile manner in accordance with the magnitude of remnant polarization, that the number of rewriting operations is about 10
12
and that the writing/reading time is substantially the same as that in DRAMs, so that there is some possibility that ferroelectric memories may change the semiconductor memory market. For that reason, manufacturers have competed with each other in developing ferroelectric memories, and 4-Mbit ferroelectric memories have been presented in societies.
FIG. 35
shows the circuit construction of a conventional ferroelectric memory. Similar to DRAMs, a memory cell comprises an NMOS transistor and a ferroelectric capacitor connected thereto in series. This memory cell configuration is called the 1T1C configuration. The difference from DRAMs is that data are stored in a nonvolatile manner by utilizing the remnant polarization of the ferroelectric capacitor. Similar to DRAMs, the configuration of a cell array may also be a folded bit configuration shown in FIG.
35
. Similar to DRAMs, the theoretical lower limit of the minimum cell size is 2F×4F=8F
2
assuming that the minimum working dimension is F.
FIG. 36
shows the operation waveform of a ferroelectric memory. In the stand-by state, bit lines BL and /BL are precharged to Vss, and plate lines PL
0
and PL
1
also have Vss. In the active state, the bit lines BL and /BL are first floated, an H level potential Vpp is applied to a selected word line WL, and the voltage of a selected plate line PL
0
is raised from Vss to Vaa. The Vaa is a common power supply voltage in the array, and usually an external power supply voltage Vdd or a voltage dropping therefrom.
At this time, a voltage is applied to the ferroelectric capacitor of the selected cell using a bit line capacity CB as a load capacity, so that a signal charge is read out to the bit lines. The potential read out to the bit lines varies in accordance with “1” or “0” of cell data. When the data is “1”, the inversion of polarization occurs, so that a large potential is generated in the bit lines. When the data is “0” the inversion of polarization does not occur, so that a small potential variation appears in the bit lines. In the case of the 1T1C configuration, a reference potential is set to be the intermediate potential between the bit line potential in the case of the data of “0” and bit line potential in the case of the data of “1”, to sense the data by means of a sense amplifier. That is, after the data is read out to the bit lines, a sense amplifier activating signal SEN is raised to H, so that the “1” data is amplified to Vaa and the “0” data is amplified to Vss.
The destructive reading of the “1” data is carried out in which the inversion of polarization occurs. In the cell of the “1” data, after the read data is sensed, the bit lines have Vaa, and the voltage between terminals of the ferroelectric capacitor is substantially zero. Thereafter, when the voltage of the plate line is returned to Vss, a voltage Vaa having the reversed polarity to the polarity during a reading operation is applied to the ferroelectric capacitor, so that the destructively read data “1” is rewritten. In the cell of the “0” data, the bit lines have Vss, so that the voltage Vaa is applied to the ferroelectric capacitor from the side of the plate line. When the voltage of the plate line is returned to Vss, the voltage between terminals of the ferroelectric capacitor is zero, the state of the memory returns to the original remnant polarization state. Thereafter, the level of the word line WL
0
is lowered, and the voltage of the bit lines BL and /BL is returned to Vss, so that the state of the memory returns to the stand-by state.
FIGS. 39A and 39B
show the locus of voltages applied to a ferroelectric capacitor during the reading and writing operations when Vaa=2.5 V, respectively. In
FIGS. 39A and 39B
, the positive axis of abscissas shows applied voltages when the potential of a plate-line-side terminal is positive, and the negative axis thereof shows applied voltages when the potential of a bit-line-side terminal is positive. The reading voltage to the bit line is derived as a voltage (on the basis of −2.5 V as a reference) at the intersection between the hysteresis curve of the ferroelectric capacitor and the straight load line of a bit line capacity CB, with respect to “0” and “1” data, respectively. The reason why this is obtained is that when the positions on Y-axis (the axis of the quantity of polarization) with respect to the start point of the locus of the ferroelectric capacitor and the start point of the straight load line are allowed to be coincident with each other, the charge outputted to the variation in polarization by applying a voltage to the ferroelectric capacitor is equal to the charge (CB×voltage) required to raise the bit line potential.
Specifically, in the example of
FIGS. 39A and 39B
, when CB=200 fF and Vaa=2.5 V, the charge read in the bit lines is about 1.5 V in the case of the “1” data and about 0.7 V in the case of the “0” data. In the case of the memory cell having the 1T1C configuration shown in
FIG. 35
, the intermediate value therebetween is set to be the reference voltage, the substantial signal quantity is 0.35 V. When a memory cell comprises two NMOS transistor and two ferroelectric capacitors (this will be hereinafter referred to as the 2T2C configuration), the signal quantity if 0.7 V.
Thus, in the ferroelectric memory, there is a problem in that the voltage applied to the ferroelectric capacitor is limited to the capacity ratio including the polarization of the ferroelectric capacitor to the bit line capacity. Specifically, in the example of
FIG. 39
, the voltage applied to the ferroelectric capacitor during reading is 2.5 V−1.5 V=1.0 V in the case of the “1” data. In the case of the “0” data, the voltage is 2.5 V−0.7 V=1.8 V. If the cell array power supply voltage Vaa is applied to the ferroelectric capacitor as it is, the difference in signal corresponding to the difference (2Pr=2×200 fF) between the quantities of remnant polarization in the cases of the “1” and “0” data can be obtained. However, the bit line capacity CB is limited, only a voltage less than Vaa is applied to the ferroelectric capacitor. In other words, only a part of remnant polarization contributes to the signal.
On the other hand, in the case of a writing (rewriting) ope

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