Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-12-18

2002-04-02

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233100, C365S201000

Reexamination Certificate

active

06366515

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly, to a dynamic semiconductor memory device operable in a refresh mode in which a refresh (restoring) of a stored data is performed. More particularly, the present invention relates to a configuration for refresh control in a dynamic semiconductor memory device.
2. Description of the Background Art
In a dynamic type semiconductor memory device (DRAM), a memory cell is constructed of one transistor and one capacitor. Information is stored in a memory capacitor in an electrical charge form. When the accumulated charge in the memory cell capacitor is lost due to leakage current or the like, a stored data therein is destroyed. Therefore, in order to prevent destruction of a stored data, a refresh operation is performed to restore a stored data in a memory cell in a prescribed period. A refresh mode includes an auto-refresh mode in which a refresh instruction is externally supplied to perform refresh of memory cell data, and a self-refresh mode in which refresh timing is automatically determined internally to perform a refresh operation.
In any of the auto-refresh mode and the self-refresh mode, a refresh address specifying a memory cell (a memory cell row) to be refreshed is generated from an internally provided counter.
FIG. 63
is a chart representing an application sequence of external signals of a conventional DRAM in the auto-refresh mode. The DRAM referred in
FIG. 63
takes in an externally applied command CMD in synchronization with a clock signal CLK, to perform an operation according to the taken in command.
First, in a clock cycle #
1
, a precharge command PRG is supplied. The precharge command PRG is taken into the DRAM at the rise of the external clock signal CLK and an internal precharge operation is performed (in this operation, the memory device is restored to an initial state).
In a next clock cycle #
2
, a no-operation command NOP is supplied as a command CMD. This is because when the internal circuitry is restored to an initial state by supplying the precharge command PRG, a so-called RAS precharge period is ensured.
In a clock cycle #
3
, an auto-refresh command ARF is supplied. The auto-refresh command ARF is taken into the memory device at a rising edge of the external clock signal CLK, and a refresh activation signal RFACT is maintained at H level internally for a prescribed period to perform refresh of memory cell data.
In a clock cycle #
4
, a no-operation command NOP is again supplied. This is done to ensure an activation period of the refresh activation signal RFACT and the precharge period following the activation period.
Subsequently, in a clock cycle #
5
, auto-refresh command ARF is again supplied. A refresh operation of memory cell data is again performed according to a refresh address generated internally following the auto-refresh command ARF. The auto-refresh command ARF is repeatedly supplied successively a prescribed number of times. A certain period is used as a refresh period and in the remaining period, data access is performed according to another command CMD so as to realize efficient data access.
FIG. 64A
is a block diagram schematically showing a configuration of a refresh address generating section. In
FIG. 64A
, the refresh address generating section includes: an address buffer
900
taking in an address signal AD supplied externally in a normal operating mode; a refresh address generating circuit
901
generating a refresh address specifying a memory cell to be refreshed; a multiplexer (MUX)
901
selecting one of an address signal from the address buffer
900
and the refresh address from the refresh address generating circuit
901
according to a select signal SEL to generate an internal address signal ADin; and a decoder
903
decoding an internal address signal ADin from multiplexer
902
to drive a word line WL provided corresponding to an addressed row to a selected state.
The selection signal SEL is activated when auto-refresh command ARF or self-refresh command SRF instructing the self-refresh mode is supplied. The multiplexer
902
selects a refresh address from the refresh address generating circuit
901
in a refresh mode (including the auto-refresh mode and the self-refresh mode) in response to activation of the selection signal SEL. The decoder
903
is activated in response to activation of a row-related activation signal RACT and decodes an internal address signal ADin to drive a word line on a selected row to a selected state when activated. The address buffer
900
is activated in accordance with a command supplied in the normal operating mode and takes in and latch an address signal supplied externally to generate an internal address signal.
FIG. 64B
is a waveform diagram representing operations in the refresh mode. When auto-refresh command ARF is supplied as a command CMD, the auto-refresh command ARF is internally taken in at the rise of the clock signal CLK (see
FIG. 63
) and a refresh activation signal RFACT is activated in accordance with the taken-in auto-refresh command ARF and the selection signal SEL is activated in response to the refresh activation signal RFACT. When the selection signal SEL is activated, the multiplexer
902
selects the refresh address from refresh address generating circuit
901
to generate an internal address signal ADin. After the internal address signal ADin becomes definite, decoder
903
activated by the row-related activation signal RACT performs a decode operation to drive a word line WL corresponding to an addressed row to a selected state.
Therefore, when an auto-refresh command ARF is supplied, a to-be-selected word line WL is driven to a selected state after elapse of time ta from the rise of a clock signal CLK or in a time tb after the row-related activation signal RACT is activated. This is because a command supplied externally is taken in at the rise of the clock signal CLK and then, an internal operation instructing signal is generated to start an internal operation.
On the other hand, when a self-refresh command SRF is supplied, selection signal SEL and refresh activation signal RFACT are activated in response to the self-refresh command SRF. The selection signal SEL maintains an active state at H level during the self-refresh mode. A row-related activation signal RACT is activated by a refresh request generated periodically from a refresh timer included in refresh address generating circuit
901
. In the self-refresh mode, multiplexer
902
already selects a refresh address from refresh address generating circuit
901
according to selection signal SEL. When a refresh request is generated, an internal address signal ADin is in the definite state; therefore, decoder
903
performs a decode operation in response to a row-related activation signal RACT to drive a selected word line WL to a selected state.
In the self-refresh mode, it is necessary to take a time tc to drive a word line WL to a selected state after activation of row-related activation signal RACT, wherein times tb and tc are equal to each other. In the auto-refresh mode, decoder
903
is required to be activated after selection signal SEL is activated, and an internal address signal ADin becomes definite, and therefore timing adjustment becomes more complex than in the self-refresh mode, leading to a problem that a row-related control signal has to be activated at different activation timings between the self-refresh mode and the auto-refresh mode. In this case, it may be possibly considered that selection signal SEL is selectively activated by a refresh request in the self-refresh mode. When selection signal SEL is driven to an active state in response to a refresh request in the self-refresh mode, however, selection signal SEL has to be charged and discharged, to increase current consumed in the self-refresh mode in which a current consumption is required to be as small as possible.
Further, Japanese Patent Laying-Open No.11-339174 discloses a techni

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