Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-11-14

2002-01-15

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S185200

Reexamination Certificate

active

06339556

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a configuration that increases the data read rate.
2. Description of the Prior Art
Since in the past, a quick access to a flash memory has been demanded similar to other forms of memory medium. According to the conventional circuit configuration, since the input impedance on the reference cell array side is kept at a constant level for all times, circumstances arise in which the input impedance on the reference cell array side and the input impedance on the main cell array side do not match with each other for some cell arrays selected on the main cell array side. As a result, it has been very difficult to realize a fast access to the main memory cell array.
FIG. 1
is a circuit diagram showing the configuration of a semiconductor memory device according to Prior Art 1. Of the impedances as seen from I-V conversion circuits (current-to-voltage conversion circuits)
2
and
3
, the impedance varies depending upon the selected sector on the main cell array side, whereas it does not vary depending upon the selected sector on the reference cell array side, as indicated in
FIGS. 4A-4B
.
In order to read data in a cell array
1
, a cell array
1
selection signal and a reference cell array selection signal are brought to high level, and a node
500
is connected to a node
700
, and a node
600
is connected to an I-V conversion circuit
3
.
A cell array N select signal (cell array select signal for controlling a cell array select N-channel transistor (N-ch Tr) corresponding to a cell array other than the cell array
1
) goes to low level, and a node
501
and a global bit line
4
go to open state. Then, a row decoder
9
of the cell array
1
selects an arbitrary word line, and its column decoder
10
selects an arbitrary sub-bit line
7
. The arbitrary sub-bit line selected is connected to the node
500
via the column decoder
10
. A row decoder
11
selects a word line connected to a reference cell gate in the reference cell array. The reference sub-bit line
8
is connected to the node
600
via a dummy decoder
12
.
Next, the operation of the Prior Art 1 semiconductor memory device will be described. By the transition of an address transaction director (ATD) signal
2
from high to low level, and the transition of a PRE signal from low to high level in a state at T=0, the I-V conversion circuits
2
and
3
are activated to start cell data read operation. The global bit line
4
and the sub-bit line
7
of the cell array
1
, and a reference global bit line
5
and the reference sub-bit line
8
of the reference cell array are charged up by the currents from the I-V conversion circuits
2
and
3
, respectively.
To describe the operation with reference to the I-V conversion circuits
2
and
3
in
FIG. 2
, the output of the NOR circuit goes to high level as a result of transition of the ATD signal from high level to low level. As the output of the NOR circuit goes to high level, the global bit line
4
and the reference global bit line
5
are connected to a power supply via an N-ch Tr
1
. In addition, as the PRE signal goes to high level, the global bit line
4
(reference global bit line
5
in the I-V conversion circuit
3
) is connected to the power supply.
A precharging circuit in the I-V conversion circuits
2
and
3
is provided for supplementing charge-up of each bit line. By the connection of the node
700
and the reference global bit line
5
to the power supply the potentials at the nodes
500
,
700
and
600
go up. When the potential reaches the threshold voltage of NOR circuit in the I-V conversion circuits
2
and
3
, the N-ch Trs
2
and
5
in the I-V conversion circuits
2
and
3
are turned off. This state represents a state in which the global bit line
4
, the sub-bit line
7
, the reference global bit line
5
and the reference sub-bit line
8
are fully charged up by the current flowing in the I-V conversion circuits
2
and
3
.
According to the conventional circuit configuration, the impedance of the global bit line
4
on the main cell array side and the impedance of the reference global bit lime
5
on the reference cell array side as seen from the I-V conversion circuits
2
and
3
are different as shown in FIG.
4
.
FIGS. 9A and 9D
are the waveform diagrams showing the waveforms of the current and voltage in respective paths. A current IgsN that flows in the global bit line
4
and a current Igs1 (=Is1) that flows in the sub-bit line
7
start charging of the capacitance of the global bit line
4
and the capacitance of the sub-bit line
7
from T=0 and complete the charging at T=1. When the charging is completed, the current IgsN flowing in the global bit line
4
goes to 0[A]. The current Igs1 flowing in the sub-bit line
7
is the cell current selected in the cell array. A current Im input to the I-V conversion circuit
2
is given by the following formula:
Current Im=IgsN+Igs1
Analogously, in the reference part, a current IgrN flowing in the reference global bit line
5
and a current Igr1 flowing in the reference sub-bit line
8
start charging the capacitance of the reference global bit line
5
and the capacitance of the reference sub-bit line
8
at T=0 and completes the charging at T=1. When the charging is completed, the current IgrN flowing in the reference sub-bit line
8
goes to 0[A]. The current Igr1 flowing in the reference sub-bit line
8
is the cell current selected in the cell array. A current Iref that is input to the I-V conversion circuit
3
is given by the following formula:
Current Iref=IgrN+Igr1.
Each of the charging currents varies according to the impedance as seen from each of the I-V conversion circuits
2
and
3
. Since the impedances on the main cell array side and the impedance on the reference cell array side differ as shown in
FIGS. 4A-4B
, the currents Im and Iref are different. In the state at T=1, the PRE signal changes from high level to low level, and the precharging circuits in the I-V conversion circuits
2
and
3
stop their operations.
Describing the operation by reference to the I-V conversion circuits
2
and
3
in
FIG. 2
, as a result of transition of the PRE signal to low level the N-ch Tr
4
in the I-V conversion circuits
2
and
3
is turned off, and the global bit line
4
(reference global bit line
5
in the I-V conversion circuit
3
) and the power supply go into an open state.
In the state at T=1, the nodes
500
,
700
and
600
are fully charged. During the period from T=1 to T=2, it is necessary for the main cell array side to transmit the current of the selected cell to Im. Since the electric charge stored on the global bit line
4
flows into Igs1, the current Im apparently goes to 0[A].
On the reference cell array side, the reference cell current Iref is transmitted to the I-V conversion circuit
3
at T=1. The transmission takes place since the reference global bit line
5
carries no parasitic capacitance and no excess charge is stored on it.
Accordingly, during the stage from T=1 to T=2, the expected current Iref is transmitted to the I-V conversion circuit
3
in its complete form, but the expected current Im is not transmitted to the I-V conversion circuit
2
in its complete form. Consequently, the outputs Vm and Vref of the I-V conversion circuits
2
and
3
give a difference potential which is not expected. If Vm and Vref are compared in this stage, there is a possibility that the comparator circuit
1
cannot output the exact information, which becomes a cause of malfunction.
During the period from T=2 to T=3, the cell current of a cell actually selected by the cell array
1
starts to flow, and the output Vm of the I-V conversion circuit
2
begins to change. It is only at the stage of T=4 that the expected difference p

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