Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1999-04-14

2002-03-05

Fears, Terrell W. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S230030

Reexamination Certificate

active

06353569

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor memory device which is suitable for high speed and low power consumption operations and to a semiconductor data processor such as a microcomputer or a microprocessor using such a semiconductor memory device.
BACKGROUND OF THE INVENTION
Employing techniques for lower power consumption is essential for elongating the lifetime of a battery in a PDA (Personal Digital Assistant) or a portable personal computer. In a high end microcomputer, too, the problem of heat generation resulting from power consumption becomes serious in the sense of deteriorating the reliability of the device.
A known technique for reducing the power consumption of a memory circuit is exemplified in the prior art by lowering the supply voltage, as disclosed on pp. 53 and 54 of 1990 Symposium on VLSI Circuit, Digest of Technical Papers (1990), which is hereinafter referred to as prior art (1).
There is another method by which a memory of smaller capacity is placed in a lower hierarchy of an architecture having a multi-hierarchy memory, as disclosed on pp. 16 and 17 of 1994 IEEE Symposium on Low Lower Electronics, Digest of Technical Papers (1994) (Prior Art 2). Generally speaking, a memory of the smaller storage capacity can be constructed to have the lower load resistance and capacity in its bit lines or the like so that it can be operated in the lower power consumption. In this example of the prior art, the power consumption is reduced by enhancing the frequency of accessing the memory of as low hierarchy as possible to have the smaller capacity, i.e., the memory of the lower power consumption.
SUMMARY OF THE INVENTION
A portable information device of high-speed and low power consumption is realized with a cache memory built-into a semiconductor data processor, such as a microprocessor, providing a high hit ratio. Since the access of an off chip memory, of which a load is large, can be decreased with a built-in type of cache memory providing a high hit ratio, the power consumption of the whole portable information device can be reduced. And, because the access of the memory of which the latency is long decreases, speed-up can be attained.
Recent trends have resulted in the storage capacity of the memory installed in a semiconductor data processor such as a microcomputer or a microprocessor to be increased. As a result, the number of memory cells connected to the bit lines of the memory array of the internal memory has increased (which enlarges the load) to increase the access time. In order to shorten this access time, therefore, it is necessary to increase the current of the memory cells. This increase in the current of the memory cells can be realized by lowering the threshold voltage of the MOS (Metal-Oxide-Semiconductor) transistors. However, the present inventors have found that the lowering of the threshold voltage brings about the following problem in a low supply voltage range of 1 V.
FIG. 14
illustrates the static noise allowance of the memory cells for the threshold voltages (Vth) of 0.5 V and 0.3 V when the supply voltage is 1 V. As illustrated in
FIG. 14
, the static noise allowance is 0.4 V for Vth=0.5 V and is 0.25 V for Vth=0.3 V. In other words, the static noise allowance is reduced by 38% if the threshold voltage is lowered by 0.2V. From the standpoint of reliability, therefore, there arises a problem that the threshold voltage of a MOS transistor composing memory cells cannot be lowered.
If, moreover, a memory of large storage capacity is used in the low voltage operation, the following problem arises, as found by the inventors.
FIG. 15
illustrates the dependency of the read rate on the supply voltage in a secondary cache memory (L2-cache) of 16 Kbytes and a primary cache memory (L1-cache) of 2 Kbytes. The pie charts show the ratios (which means the memory cell current ability) of the time period till a predetermined potential difference arises in the bit line pairs (that is, the time period till the sense amplifier can be started, which will be hereinafter referred to as the memory cell time) to the entire read time period. In the supply voltage range as high as 2.5V or the like, as shown in
FIG. 15
, the portion, which is occupied by the memory cell time period of the primary cache memory and the secondary cache memory, is as low as 30% or less. In the supply voltage range as low as 1 V or the like, however, the portion, which is occupied by the memory cell time period of the secondary cache memory, exceeds 50%, as shown in FIG.
15
. In short, in order to improve the read time period in the supply voltage range as low as 1 V or the like, it is necessary to increase the current of the memory cells. As described above, however, the threshold voltage of a MOS transistor composing memory cells cannot be lowered.
In the prior art (1), the memory which is operable at the supply voltage of 1 V is described, but there is no description of the aforementioned problem which has been found out by the inventors.
As described in connection with the prior art (2), moreover, the method of arranging a plurality of memories of small storage capacity requires the use of a peripheral circuit such as a decoder for each memory, which brings about the problem enlarging the circuit scale. On the other hand, when the power consumed by the memory array itself can be reduced, there arises a problem that the power consumed by the peripheral circuit or the like, due to the arrangement of the plurality of memories, increases.
For the known techniques, therefore, it is difficult to solve all of the considerations involving attempts at reducing power consumption, to speed up the operations and to reduce the circuit scale.
An object of the present invention is to provide a semiconductor memory device capable of operating at high speed and with low power consumption, and a semiconductor data processing device having such a semiconductor memory device packaged therein.
Another object of the present invention is to provide a memory structure/circuit capable of solving the aforementioned problem of the reduction of speed due to the low voltage.
Yet another object of the present invention is to provide a memory structure/circuit capable of solving the problem of the increase in the circuit scale when memory arrays are connected together in a hierarchy.
A further object of the present invention is to provide a cache memory which is suited to be packaged in a data processing device such as a microprocessor.
A representative one of the inventions disclosed herein will be briefly summarized in the following.
(1) A semiconductor memory device has: a first memory array (MAS) including a plurality of word lines (WS
1
and so on), a first bit line pair (BS
1
, BSB
1
and so on), and a plurality of memory cells (M) arranged at the intersections of the plurality of word lines and the first bit line pair; a second memory array (MAF) including a plurality of word lines (WF
1
and so on), a second bit line pair (BF
1
, BFB
1
and so on), and a plurality of memory cells (M) arranged at the intersections of the plurality of word lines and the second bit line pair; a sense amplifier (SA
1
and so on) for amplifying a signal outputted to the second bit line pair; and switch means (HS
1
) for controlling the connection between the first bit line pair and the second bit line pair, wherein a signal outputted to the first bit line pair is transmitted through the switch means and the second bit line pair to the sense amplifier.
(2) A semiconductor memory device has: a first memory array (MAS) including a plurality of word lines (WS
1
-WSp), a first bit line pair (M) arranged at the intersections of the plurality of word lines and the first bit line pair; and a second memory array (MAF) including a plurality of word lines (WF
1
-WFq), a second bit line pair (BF
1
, BFB
1
-BFn, BFBn), and a plurality of memory cells (M) arranged at the intersections of the plurality of word lines and the sec

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2871574