Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-08-21

2002-01-15

Jackson, Jr., Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S390000, C257S391000, C257S903000, C257S904000, C257S908000, C365S149000, C365S189040

Reexamination Certificate

active

06339240

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to a semiconductor memory device and a method for manufacturing the same, and more particularly to a semiconductor memory device enabling a reduction of a memory cell in size and a method for manufacturing the same.
2. Description of the Related Art
Since unit cell of DRAM(Dynamic Random Access Memory) basically consists of one transistor and one capacitor, there is benefit that an area occupying the unit cell thereof is small. For manufacturing such DRAM, should be performed four-times polysilicon deposition process; a first polysilicon deposition process for a word line, a second polysilicon deposition process for a bit line, a third polysilicon deposition process for a storage node of a capacitor and a fourth polysilicon deposition process for a plate node of the capacitor. Therefore, the manufacturing process of the DRAM is complicated. Further, a read access port and a write access port both are connected to one data line, so an operation of the DRAM as a logic device is complicated.
In order to remove the above mentioned drawbacks, a method for manufacturing the DRAM by one-step polysilicon deposition process had been proposed.
In
FIG. 1
, DRAM has a pass transistor for writing, a pass transistor for reading, a storage transistor, a capacitor, word lines for driving the pass transistors and bit lines intersecting the word lines for a data-in and data- out. M
1
represents the pass transistor for writing, M
2
the storage transistor and M
3
the pass transistor for reading. Word line WL
1
for reading is connected to a gate of the read pass transistor M
3
. Word line WL
2
for writing is connected to a gate of the write pass transistor M
1
. Bit line BL
1
for writing is connected to a source of the write pass transistor M
1
. Bit line BL
2
for reading is connected to a source of the read pass transistor M
3
. A drain of the write pass transistor M
1
is connected to a gate of the storage transistor M
2
. A drain of the storage transistor M
2
is connected to a drain of the read pass transistor M
3
. A source of the storage transistor is connected to a Vss voltage terminal. A parasitic capacitor C
1
is formed between the drain of the write pass transistor and the gate of the storage transistor. As a capacitance of the capacitor C
1
is increased, an amount of data stored in DRAM is increased.
A semiconductor memory device including a circuit of
FIG. 1
is designed to determine that if Vss voltage level is detected through the bit line, data is stored in the DRAM cell or if the voltage level over Vss voltage level is detected, no data is in the DRAM cell.
In writing operation, the write word line WL
2
is accessed and the write pass transistor M
1
is turned on. Accordingly, data at the write bit line BL
1
is, through the write pass transistor M
1
, stored in the capacitor C
1
.
In reading operation, the read word line WL
1
is accessed and the read pass transistor M
2
is turned on. The storage transistor M
2
is turned on or off in response to data stored in the capacitor C
1
. If data is previously stored in the capacitor C
1
, the storage transistor C
1
is turned on and the Vss voltage level is detected at the read bit line BL
2
. Otherwise, if no data is stored in the capacitor C
1
, the storage transistor M
2
is turned off and the voltage level over Vss voltage level is sensed at the read bit line BL
2
.
FIG. 2
is a view showing a layout of DRAM in FIG.
1
. Y
1
and Y
2
each represents DRAM cell unit area. A
1
stands for a first active region on which the storage transistor M
2
and the read pass transistor M
3
are formed. A
2
stands for a second active region on which the write pass transistor M
3
is formed.
4
A indicates a gate of the write pass transistor M
1
,
4
B a gate of the storage transistor M
2
and
4
C a gate of the read pass transistor M
3
. Particularly, a width of the gate of the storage transistor M
2
is proportional to the capacitance of the capacitor C
1
, so the width of the gate of the storage transistor M
2
is designed larger than that of gates of the read pass transistor M
3
and the write pass transistor M
1
. The reference
2
designates an element separating region isolating the first active region and the second active region. The reference
5
indicates both side portions of the gates
4
A,
4
B and
4
C in the active regions A
1
, A
2
. C-
1
is a contact hole between the source of the read pass transistor M
3
and the read bit lines WL
1
. C-
2
is a contact hole between the source of the storage transistor M
2
and the Vss voltage terminal. C-
3
is a contact hole between the source of the write pass transistor M
1
and the bit line BL
1
. C-
4
is a contact hole between the gate of the storage transistor M
2
and the drain of the write pass transistor M
1
.
FIG. 3
is a sectional view along III-III′ of FIG.
2
. With reference to
FIG. 3
, a method for manufacturing DRAM as shown in FIG.
1
and
FIG. 2
will be explained.
A device isolating region
2
for separating the first active region A
1
and the second active region A
2
is formed on a part of the semiconductor substrate
1
. A gate oxide and polysilicon are successively deposited over the substrate
1
, and then patterned in a known etching method to form gate oxides
3
A,
3
B,
3
C and gates
4
A,
4
B,
4
C. As mentioned above, a width of the gate
4
B of the storage transistor M
2
is larger than those of the gates
4
A,
4
C of the other transistors M
1
, M
3
. Thereafter, N type of impurity ions are implanted to the substrate on which the gates are formed, forming junction regions
5
-
1
,
5
-
2
,
5
-
3
,
5
-
4
,
5
-
5
of the respective transistor. The junction region
5
-
2
is a common junction region of the storage transistor M
2
and the read pass transistor M
3
.
An insulating interlayer
6
provided with contact holes C-
1
, C-
2
, C-
3
exposing the junction regions
5
-
1
,
5
-
3
,
5
-
5
, is formed on the resultant having the transistors M
1
, M
2
, M
3
. Thereafter, metal wires
7
-
1
,
7
-
2
,
7
-
3
contacting with the junction regions via contact holes are formed.
As known from the above, in order to produce the DRAM having three transistors as shown in
FIG. 2
, four-contacts holes C-
1
, C-
2
, C-
3
, C-
4
should be required. Accordingly, area for such DRAM is increased, so an integrated density of the semiconductor device is degraded.
Further, since a pitch between the metal wires
7
-
1
,
7
-
2
,
7
-
3
is smaller and smaller with the high integrated density of the semiconductor device, a reliability of the semiconductor device is debased.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a semiconductor device improving a reliability thereof, with satisfying a high integrated density thereof and a method for manufacturing the same.
A semiconductor memory device according to a view of the present invention so as to accomplish the object of the present invention, comprises a first word line, a second word line, a first bit line, a second bit line and a first passer for passing a data loaded on the first bit line by a turn-on thereof when the first word line is accessed. The semiconductor memory device further has a storage for storing a data outputted from the first passer, a second passer for transferring a data stored in the storage to the second bit lines by turn-on thereof when the second word line is accessed and a supplier for providing a substrate voltage for the storage.
In an embodiment, the first word line and the second word line are respectively for writing and reading. The first bit line and the second bit line are respectively for writing and reading. The first passer includes a NMOS transistor and the supplier includes a NMOS transistor with P type of impurity region. The second passer and the storage each has NMOS transistor. In detail, a gate, a source and a drain of the first passer are respectively connected to the write word line, the write bit line and gate of the storage. A g

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