Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-06-15

2002-01-22

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Parallel read/write

C365S221000, C365S230090

Reexamination Certificate

active

06341096

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor memory device, and specifically to a semiconductor memory device which sequentially designates address values in a memory, such as a FIFO (First-In-First-Out) memory, according to an external clock, and which performs an operation of returning to a specified address during reset.
2. Description of Related Art
FIG. 15
is a block diagram of a semiconductor memory device
600
of a conventional clock-synchronized type.
FIG. 15
shows a FIFO memory
601
and a circuit which designates a read address of the FIFO memory
601
. In order to designate a read address of the FIFO memory
601
, a read controller
602
, a read counter
603
, and a delay circuit
604
are provided.
A read clock signal RCK and a reset signal RRS are input to the read controller
602
. The read controller
602
is synchronized with the read clock signal RCK and generates a read counter clock signal CNT and a memory read access signal CS. Furthermore, the read controller
602
detects a LOW level of the reset signal RRS and generates a read counter reset signal RS.
As the read counter
603
counts up the read counter clock signal CNT and updates address values one by one, the read counter
603
is synchronized with the read clock signal CNT and generates a read address signal An. The FIFO memory
601
is a clock-synchronized type memory which latches the address signal An at the fall of the memory read access signal CS. Additionally, the purpose for generating a memory read access signal CS′, which has been delayed in the delay circuit
604
, will be described later.
FIG. 16
is a timing chart relating to a reading operation of the semiconductor memory device
600
.
At time t1 shown in
FIG. 16
, an external clock signal RCK rises. In synchronization with the rise of this external signal RCK, the memory read access signal CS falls at time t2, and the FIFO memory
601
enters into a reading state.
At this time, the read counter
603
holds “N” as the address signal An as shown in FIG.
16
.
The FIFO memory
601
latches the address signal An at the fall of the memory read access signal CS at time t2. Therefore, the FIFO memory
601
can perform an N read cycle, which reads data Yn corresponding to the address signal An (address value N) which has been latched at time t2.
However, actually, the memory read access signal CS′ is generated, which is delayed from the memory read access signal CS by the time interval tdly of
FIG. 16
in the delay circuit
604
, and the address signal An is latched at the fall of the signal CS′. Because of this, data Yn is read from the FIFO memory
601
after passage of a specified access time interval tacs from the starting time t1 of the N read cycle. This access time interval tacs will be discussed later.
When the external clock signal RCK falls at time t3 after the data Yn is read, the counter clock signal CNT falls at time t4, and the memory read access signals CS and CS′ rise. The memory access is completed as the memory read access signals CS, CS′ rise. Meanwhile, the read counter
603
counts up at the fall of the counter clock signal CNT, outputs the value N+1 as the address signal An, which is the output, and prepares for the following read cycle.
Here, in
FIG. 16
, after the external clock signal RCK falls at time t3, the reset signal RRS changes to LOW at time t5 before the following rising time t6.
In the reset cycle in which the reset signal RRS becomes LOW, the FIFO memory
601
needs to implement a read access to the memory address 0 within the cycle.
Because of this, the counter reset signal RS falls in synchronization with the rise of the clock signal RCK at time t6 as shown in
FIG. 16
, and the address signal An from the read counter
603
at time t7 becomes “0”.
Here, in the above-mentioned N read cycle, the timing at which the address signal An from the read counter
603
becomes “N” is synchronized with the fall of the clock signal RCK a half cycle before time t4 as shown in FIG.
16
. That is, the timing at which the address signal An from the read counter
603
becomes “N” is set to be prior to entering the N read cycle.
However, in the reset cycle, the timing at which the address signal An from the read counter
603
becomes “0” is set at the starting point of the reset cycle.
In this case, when the address signal An is latched at the timing of time t7, at which time the memory read access signal CS falls, the address signal An has not yet been changed from “N” to “0”. Thus, the address setup time cannot be secured, or is difficult to determine, in the reset cycle.
In order to avoid this problem, as mentioned above, the memory read access signal CS′ is generated in which the memory read access signal CS is delayed by the time interval tdly of
FIG. 16
in the delay circuit
604
, and the address signal An is latched at the fall (time t8) of the signal CS′.
However, if the memory read access signal CS is delayed in the delay circuit
604
, the address latch timing is delayed by the time interval tdly in a normal cycle, as well as in the reset cycle, and the access time interval tacs of the FIFO memory
601
has increased as shown in FIG.
16
.
In particular, when the number of words of the FIFO memory
601
increases, a circuit area occupied by the read counter
603
becomes large, and the length of the wiring to implement the reset cycle becomes long. This means that the signal delay is prolonged within the read counter
603
and on the output wiring, and that the time interval during which address 0 from the read counter
603
is transmitted to the FIFO memory
601
further increases.
SUMMARY OF THE INVENTION
As a result, the above-mentioned problems significantly appear.
Therefore, an object of this invention is to provide a semiconductor memory device which secures the address setup time in the reset cycle, which shortens the memory access time in the normal cycle and in the reset cycle, and which can be operated at high speed.
Another object of this invention is to provide a semiconductor memory device which can be operated at even higher speed by making the timing at which the read address signal in the reset cycle is changed to a specified address value, such as address 0, asynchronous with the read clock signal.
A semiconductor memory device of this invention has
a memory which reads data in synchronization with a read clock signal,
a read controller which synchronizes with the read clock signal, generates a read counter clock signal and a memory read access signal, and generates a read counter reset signal which becomes active in synchronization with the read clock signal after the reset signal becomes active,
a read counter which sequentially generates first read address signals with different address values in synchronization with the read clock signal and which is reset when the read counter reset signal is active, and
a read address setting circuit which outputs second read address signals to the memory, based on at least the first read address signals from the read counter and the reset signal.
The address values of the second read address signals from the read address setting circuit are set based on the address values of the first read address signals when the reset signal is inactive, and the reset signal is set at a specified address value regardless of the logic of the first read address signals when the reset signal is active.
According to this invention, the address values of the second read address signals supplied to the memory are normally set based on the first read address signals from the read counter in a read cycle. Meanwhile, in the reset cycle, the address values of the second read address signals supplied to the memory are set in a system different from that in the read counter. Because of this, reset is activated after the counter reset signal becomes active, and a specified address value is set in the reset cycle, in which an internal delay is generated, without depending on the o

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