Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-01-25

2002-05-21

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S200000, C365S225000

Reexamination Certificate

active

06392945

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device such as ROM (read only memory) and RAM (random access memory). In particular, the present invention relates to techniques for a miniaturized semiconductor memory device to redress faults in word lines caused by leaks, broken connections and the like.
2. Description of the Related Art
It is well know that, in order to redress faults present within a memory cell array forming a semiconductor memory device and increase the yield, it is effective to form the memory cell array as a redundant structure.
An example of a redundant structure is one in which, in RAM and the like, lines (row lines and column lines) of spare memory cells are provided in advance inside the semiconductor memory device during the manufacturing process and, if it is discovered during the testing process that there are faults in the memory cell array, the faults are redressed by replacing the line containing the faults with the spare row line or column line.
However, it is not possible to employ a redundant structure such as that described above in mask ROM and the like. In mask ROM, because the memory cell data is programmed in the manufacturing process, as the locations where faults are generated are not discovered in advance during the manufacturing process, it is not possible to program spare lines in the manufacturing process. Namely, even if it is discovered afterwards in the testing process that there are faults in the memory cell array, it is not possible to replace the faulty portion with a spare line as it is with RAM.
Therefore, in mask ROM and the like, instead of providing spare lines, faults are redressed by error correction using ECC (error checking and correcting code). By performing this type of error correction, if the faults are of several bits size, error redress is possible without overly increasing the ECC bit number. Moreover, the more the ECC bit number is increased, the more bit number errors it is possible to correct. However, as increasing the ECC bit number is directly related to increased chip size, this is not preferable. Furthermore, naturally, because there is not an unlimited number of areas where ECC allocation is possible, when there is a large number of faulty memory cells, it is not possible to correct all errors. In such cases, it is necessary to discard chips whose faults were the object of correction measures as faulty chips, which results in a lower yield.
However, one of the reasons why many memory cells become faulty is because of minute leaks and broken connections arising on a word line as a result of malfunctions in the manufacturing process. Firstly, a description will be given of what happens when leaks occur on a word line, with reference made to
FIGS. 11A
to
11
C. In
FIG. 11A
, it will be assumed that, in the ROM, a single driver
200
simultaneously drives four word lines
201
1
to
201
4
. In the same diagram, a leak is shown as occurring at the point X on the word line
201
4
.
Here, the reason why a single driver is driving a plurality of word lines is because it is becoming difficult to provide a driver for each word line due to the continuing miniaturization of semiconductor memory devices. Namely, through miniaturization, because the size of the memory cells becomes smaller compared with the size of the driver, the trend is for the size of the driver to become relatively larger. In ROM and the like, in particular, because a memory cell can be formed from a single transistor, the size of the driver becomes larger by that amount as compared with the size of the memory cell. Therefore, the problem arises that, if a driver is provided for each word line, the surface area increases. As a result, the structure in which a single driver is provided for a plurality of word lines is currently the most common one.
As is shown in
FIG. 11A
, when malfunctions arise due to various reasons in the manufacturing process, in some cases, it is equivalent to a high resistance resistive element being present between the ground and the word line
201
4
on the substrate or the chip. In such cases, a leak occurs at the point X shown in FIG.
11
A. Here,
FIG. 11B
shows an equivalent circuit corresponding to the structure shown in
FIG. 11A
, specifically, an equivalent circuit for when the driver
200
supplies a high level (hereinafter abbreviated to “H”) is shown only for the word line
201
4
.
In
FIG. 11B
, the symbol Vi indicates the potential of the word line
201
4
in the vicinity of the output end (namely, the end near the word line) of the driver
200
; the symbol Vxb indicates the potential of the word line
201
4
at the point X in
FIG. 11A
; the symbol Vb indicates the potential at the far end of the word line
201
4
as seen from the driver
200
; the symbol Ra indicates a resistive element corresponding to resistance values from the near end of the word line
201
4
to the X point; the symbol Rb indicates a resistive element corresponding to resistance values from the X point to the far end of the word line
201
4
; and the symbol Rx indicates a resistive element corresponding to resistance values from the X point to the substrate (or ground wiring).
FIG. 11C
shows the relationship between the potential on the word line and the distance (horizontal axis) taking the output end of the driver
200
as a reference with attention centering on the word line
201
4
. Here, when memory data is read from a memory cell, the memory cell that is being read is turned on or off (referred to below as “on cells” and “off cells”) in accordance with the memory data, and from that it is determined whether or not current is flowing through the bit line. Here, a bit line is also called a digit line or a data line. As a result, it is possible to determine the data stored in the relevant memory cell. In order to do this, it is necessary to set the word line potential supplied to the gate terminal of the cell transistor forming the memory cell to the necessary level (namely, to the threshold voltage of the cell transistor) or higher. The “Vt of On cell” shown in
FIG. 11C
represents this threshold voltage.
As is shown in
FIG. 11C
, the potential of the word line
201
4
from the vicinity of the Xt point (omitted from
FIG. 11B
) positioned nearer the driver
200
than is the X point is less than the “Vt of On cell” due to the effects of the leakage problems at the X point in FIG.
11
A. Moreover, beyond (i.e. towards the far end side) the Xt point as well, the potential of the word line
201
4
continues to fall up to the X point. At the X point in
FIG. 11A
, the potential of the word line
201
4
changes to the potential Vxb, and at the far end of the word line
201
4
, the potential of the word line
201
4
changes to the potential Vb which is substantially equivalent to the potential Vxb.
In this way, the gate potentials of the cell transistors forming each memory cell connected to the word line
201
4
do not reach the threshold value on the far end side of the Xt point. Therefore, these memory cells end up being always off which results in it being impossible to read of all of these memory cells. As described above, even if only a very minute leak occurs in a word line, reading of all of the memory cells towards the far end side of the location where the leak occurs becomes impossible. Accordingly, if the leak occurs at the near end of the word line, then all of the memory cells connected to that word line end up becoming unreadable.
Next, a description will be given of what happens when a broken connection occurs on a word line with reference made to
FIGS. 12A
to
12
C. In these figures, the same elements as shown in
FIGS. 11A
to
11
C are shown when a broken connection has occurred. Accordingly, in
FIGS. 12A
to
12
C, the same structural elements and signal names as were shown in
FIGS. 11A
to
11
C have the same descriptive symbols allocated thereto.
In
FIG. 12A
, it will be assumed that a broken connection has occurred at the point X on the

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