Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-10-10

2002-03-05

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S185200, C365S185250

Reexamination Certificate

active

06353560

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Filed of the Invention
The present invention to a semiconductor memory device, and more specifically the present invention relates to a semiconductor memory device so configured as to generate a precharge voltage in the case where a precharge method is used for memory cell reading.
2. Description of the Related Art
For a memory cell reading method in semiconductor memory devices such as MROMs (Mask Read Only Memory), precharge methods have been conventionally proposed. An example will be described below in which a MROM is read by a precharge method. According to the precharge method, a bit line is connected to a memory cell transistor, which is either an ON transistor or an OFF transistor, wherein the bit is first charged to a precharge level for a certain period of time (hereinafter, this time is referred to as a precharge period). After the charging is completed, a sense circuit detects the discharge waveform of the bit line and determines whether the memory cell transistor connected to the bit line is an ON transistor or an OFF transistor.
Memory cell transistors are fabricated by, e.g., an ion injection method, and for making them ON transistors or OFF transistors, for example, the following two methods are used:
In one method, the threshold voltages of transistors are changed so as to form ON transistors which turn to the ON state by applying a voltage VI to their gates and OFF transistors which turn to the OFF state by applying the same voltage V
1
to their gates. In the other method, the threshold voltage is not changed. OFF transistors are formed by physically forming an electrical isolation between their sources and drains. For ON transistors, transistors in which the current flows between their sources and drains are used.
FIG. 5
shows a connection example between a precharge circuit and a memory cell transistor in a conventional semiconductor memory device
200
. According to the semiconductor memory device
200
in
FIG. 5
, a precharge circuit includes: a reference voltage generating circuit
30
for generating a reference voltage for charging a bit line
11
; and a charge transistor N
1
formed of an Nch (N-channel) transistor. An inverter INV
1
is used in the reference voltage generating circuit
30
. The output of the inverter INV
1
is applied to the gate of the charge transistor N
1
and the drain of the charge transistor N
1
is connected to a supply voltage VCC. The source of the charge transistor N
1
is connected to the input terminal of the inverter INV
1
. The reference voltage generating circuit
30
including the inverter INV
1
and a charge transistor N
1
together form a feed back bias circuit. The reference voltage generated by the feedback bias circuit is determined by controlling the inversion voltage of the inverter INV
1
.
The drain of the Nch transistor NTR
1
is connected via the bit line
11
to the source of the charge transistor N
1
. The drain of a memory cell transistor M
1
is connected to the source of the Nch transistor NTR
1
. and the source of the memory cell transistor M
1
is connected to the drain of the Nch transistor NTR
2
. A sense circuit
20
is connected to the bit line
11
between the charge transistor N
1
and the Nch transistor NTR
1
.
The case will now be described where the memory cell transistor M
1
of such a semiconductor memory device is an OFF transistor (i.e., no current flows between the source and drain even if the gate voltage is in the H (High) level) and the gate voltages input to the respective gates of the Nch transistor NTR
1
, the memory cell transistor M
1
, and the Nch transistor NTR
2
are all in the H level. If the bit line
11
connected to the source of the charge transistor N
1
is initially in the L (Low) level, the L level is input to the input of the inverter INV
1
of the reference voltage generating circuit
30
. When the input of the inverter INV
1
turns to the L level, the output of the inverter INV
1
turns to the H level, and then the H level is input to the gate of the charge transistor N
1
. The supply voltage VCC, which is connected to the drain of the charge transistor N
1
, is then applied to the bit line
11
.
Since the memory transistor M
1
is an OFF transistor, no current path to the GND is provided, and the bit line
11
is charged through the charge transistor N
1
.
When the bit line
11
is charged to a voltage exceeding the inversion voltage of the inverter INV
1
, the output of the inverter INV
1
turns to the L level and the charge transistor N
1
turns to the OFF state. The potential of the bit line
11
then decreases through a spontaneous discharge or the like, and when the potential of the bit line
11
becomes lower than the inversion voltage of the inverter INV
1
, the output of the inverter INV
1
turns again to the H level and the N
1
transistor turns to the ON state so as to start the charging of the bit line
11
.
By repeating such operations, the bit line
11
is stabilized at a predetermined voltage close to the inversion voltage of the inverter INV
1
, i.e., the precharge voltage.
In the case where the memory cell transistor M
1
is an ON transistor, and the respective gates of the Nch transistor NTR
1
, memory cell transistor N
1
, and the Nch transistor NTR
2
are all in the H level, the bit line
11
is connected to GND via the Nch transistor NTR
1
, the memory cell transistor M
1
, and the Nch transistor NTR
2
.
When the performance of the charge transistor N
1
is low (i.e., the ON resistance is high), the voltage of the bit line
11
can be differentiated between the case where the memory cell transistor M
1
is an ON transistor and the case where the memory cell transistor M
1
is an OFF transistor. The sense circuit
20
reads the voltage of the bit line
11
and determines whether or not the memory cell transistor M
1
is an ON transistor or an OFF transistor.
In recent years, however, the size of memory cells has been significantly reduced and thus the performance (i.e., the current driving performance) of memory cell transistor M
1
has declined (i.e., the ON resistance has been higher). This causes the difference of the potentials to become small between of the bit line
11
connected to an ON transistor and the bit line
11
connected to an OFF transistor, and therefore, the sense circuit
20
may not be able to read the difference if the current driving performance of the charge transistor N
1
is high. On the other hand, if the performance of the charge transistor N
1
is low, the time required to charge the bit line
11
to the precharge voltage is extended, which may prevent a faster reading of the memory cells when the parasitic capacitance of the bit line
11
is large.
In order to solve these problems, a semiconductor memory device
300
shown in
FIG. 6
has been proposed. Throughout the drawings, like components are denoted by like reference numerals. The semiconductor memory device
300
has the same configuration as the semiconductor memory device
200
in
FIG. 5
, except that a high performance (i.e., a low ON resistance) Nch charge transistor N
2
is connected to the Nch charge transistor N
1
and an Nch transistor NTR
0
is connected between the Nch charge transistor N
2
and the bit line
11
. The gate of the Nch charge transistor N
2
is connected to the gate of the Nch charge transistor N
1
, and the drain of the Nch charge transistor N
2
is connected to the supply voltage VCC. The source of the Nch charge transistor N
2
is connected to the drain of the Nch transistor NTR
0
and the source of the Nch transistor NTR
0
is connected to the bit line
11
.
The Nch transistor NTR
0
is turned ON/OFF by signals generated in a circuit generally known as an ATD circuit (address transition detection circuit). The period while the Nch transistor NTR
0
is ON corresponds to the precharge period, during which the bit line
11
is charged.
According to the semiconductor memory device
300
, the bit line
11
is charged quickly during the precharge period by the Nch charge transistor N
2
. When the precha

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